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authorGuenter Roeck <linux@roeck-us.net>2019-05-23 14:47:44 +0100
committerPeter Maydell <peter.maydell@linaro.org>2019-05-23 14:47:44 +0100
commit59520dc65e5ddb7bdc1a8b7bedd4b58eb76b068b (patch)
treefacafa692bb3802a3f4712f59b886adafa47309f /hw/arm
parente12a0dd28d07be556a1ce1543a9c1e281f931e8c (diff)
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hw/arm/exynos4210: Add DMA support for the Exynos4210
QEMU already supports pl330. Instantiate it for Exynos4210. Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi: / { soc: soc { amba { pdma0: pdma@12680000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12680000 0x1000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; }; pdma1: pdma@12690000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12690000 0x1000>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; }; mdma1: mdma@12850000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12850000 0x1000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MDMA>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <1>; }; }; }; }; Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190520214342.13709-4-philmd@redhat.com [PMD: Do not set default qdev properties, create the controllers in the SoC rather than the board (Peter Maydell), add dtsi in commit message] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm')
-rw-r--r--hw/arm/exynos4210.c26
1 files changed, 26 insertions, 0 deletions
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index 0bf6113..f942ed2 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -96,6 +96,11 @@
/* EHCI */
#define EXYNOS4210_EHCI_BASE_ADDR 0x12580000
+/* DMA */
+#define EXYNOS4210_PL330_BASE0_ADDR 0x12680000
+#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000
+#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000
+
static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
0x09, 0x00, 0x00, 0x00 };
@@ -160,6 +165,19 @@ static uint64_t exynos4210_calc_affinity(int cpu)
return (0x9 << ARM_AFF1_SHIFT) | cpu;
}
+static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
+{
+ SysBusDevice *busdev;
+ DeviceState *dev;
+
+ dev = qdev_create(NULL, "pl330");
+ qdev_prop_set_uint8(dev, "num_periph_req", nreq);
+ qdev_init_nofail(dev);
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, base);
+ sysbus_connect_irq(busdev, 0, irq);
+}
+
Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
{
Exynos4210State *s = g_new0(Exynos4210State, 1);
@@ -410,5 +428,13 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
s->irq_table[exynos4210_get_irq(28, 3)]);
+ /*** DMA controllers ***/
+ pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32);
+ pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
+ pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
+
return s;
}