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| author | Peter Maydell <peter.maydell@linaro.org> | 2013-04-19 11:15:20 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-04-19 11:15:20 +0100 |
| commit | a2bff788d2316c037ce5ab72468b3fda1a0527a1 (patch) | |
| tree | cb49ee0910d07c8e1749deb9befe30ee87d3f91f /hw/arm | |
| parent | 7468d73ac9a514b33c0c2797a1238db11163b23b (diff) | |
| download | qemu-a2bff788d2316c037ce5ab72468b3fda1a0527a1.zip qemu-a2bff788d2316c037ce5ab72468b3fda1a0527a1.tar.gz qemu-a2bff788d2316c037ce5ab72468b3fda1a0527a1.tar.bz2 | |
arm/realview: Fix mapping of PCI regions
Fix the mapping of the PCI regions for the realview board, which were
all incorrect. (This was never noticed because the Linux kernel
doesn't actually include a PCI driver for the realview boards.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Paul Brook <paul@codesourcery.com>
Diffstat (limited to 'hw/arm')
| -rw-r--r-- | hw/arm/realview.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/hw/arm/realview.c b/hw/arm/realview.c index df907d1..8f561c2 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -218,9 +218,9 @@ static void realview_init(QEMUMachineInitArgs *args, busdev = SYS_BUS_DEVICE(dev); qdev_init_nofail(dev); sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */ - sysbus_mmio_map(busdev, 1, 0x61000000); /* PCI self-config */ - sysbus_mmio_map(busdev, 2, 0x62000000); /* PCI config */ - sysbus_mmio_map(busdev, 3, 0x63000000); /* PCI I/O */ + sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */ + sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */ + sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */ sysbus_connect_irq(busdev, 0, pic[48]); sysbus_connect_irq(busdev, 1, pic[49]); sysbus_connect_irq(busdev, 2, pic[50]); @@ -304,12 +304,12 @@ static void realview_init(QEMUMachineInitArgs *args, /* 0x58000000 PISMO. */ /* 0x5c000000 PISMO. */ /* 0x60000000 PCI. */ - /* 0x61000000 PCI Self Config. */ - /* 0x62000000 PCI Config. */ - /* 0x63000000 PCI IO. */ - /* 0x64000000 PCI mem 0. */ - /* 0x68000000 PCI mem 1. */ - /* 0x6c000000 PCI mem 2. */ + /* 0x60000000 PCI Self Config. */ + /* 0x61000000 PCI Config. */ + /* 0x62000000 PCI IO. */ + /* 0x63000000 PCI mem 0. */ + /* 0x64000000 PCI mem 1. */ + /* 0x68000000 PCI mem 2. */ /* ??? Hack to map an additional page of ram for the secondary CPU startup code. I guess this works on real hardware because the |