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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-02-26 17:20:06 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-26 17:20:06 +0000 |
| commit | 4cc35614a056839df8b0675cd16f55e758cd570d (patch) | |
| tree | 0a8500d333df4d8e1641abaf4944e9cf10a76425 /hw/arm/pxa2xx.c | |
| parent | 1ed69e82b8f1dc69eb4c3e556a6417885a5dd49c (diff) | |
| download | qemu-4cc35614a056839df8b0675cd16f55e758cd570d.zip qemu-4cc35614a056839df8b0675cd16f55e758cd570d.tar.gz qemu-4cc35614a056839df8b0675cd16f55e758cd570d.tar.bz2 | |
target-arm: Store AIF bits in env->pstate for AArch32
To avoid complication in code that otherwise would not need to
care about whether EL1 is AArch32 or AArch64, we should store
the interrupt mask bits (CPSR.AIF in AArch32 and PSTATE.DAIF
in AArch64) in one place consistently regardless of EL1's mode.
Since AArch64 has an extra enable bit (D for debug exceptions)
which isn't visible in AArch32, this means we need to keep
the enables in env->pstate. (This is also consistent with the
general approach we're taking that we handle 32 bit CPUs as
being like AArch64/ARMv8 CPUs but which only run in 32 bit mode.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'hw/arm/pxa2xx.c')
| -rw-r--r-- | hw/arm/pxa2xx.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 5579036..904277a 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -272,8 +272,8 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, goto message; case 3: - s->cpu->env.uncached_cpsr = - ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; + s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC; + s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I; s->cpu->env.cp15.c1_sys = 0; s->cpu->env.cp15.c1_coproc = 0; s->cpu->env.cp15.ttbr0_el1 = 0; |