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authorPeter Maydell <peter.maydell@linaro.org>2020-07-27 20:34:58 +0100
committerPeter Maydell <peter.maydell@linaro.org>2020-08-03 17:55:31 +0100
commitce4f70e81ed23c93ff39234672aff33114532640 (patch)
treec746d4681500e8d7f472c4823cee9c8242013c70 /hw/arm/nrf51_soc.c
parent88a90e3de6ae99cbcfcc04c862c51f241fdf685f (diff)
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hw/arm/nrf51_soc: Set system_clock_scale
The nrf51 SoC model wasn't setting the system_clock_scale global.which meant that if guest code used the systick timer in "use the processor clock" mode it would hang because time never advances. Set the global to match the documented CPU clock speed for this SoC. This SoC in fact doesn't have a SysTick timer (which is the only thing currently that cares about the system_clock_scale), because it's a configurable option in the Cortex-M0. However our Cortex-M0 and thus our nrf51 and our micro:bit board do provide a SysTick, so we ought to provide a functional one rather than a broken one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200727193458.31250-1-peter.maydell@linaro.org
Diffstat (limited to 'hw/arm/nrf51_soc.c')
-rw-r--r--hw/arm/nrf51_soc.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index 45e6cc9..e15981e 100644
--- a/hw/arm/nrf51_soc.c
+++ b/hw/arm/nrf51_soc.c
@@ -32,6 +32,9 @@
#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
+/* HCLK (the main CPU clock) on this SoC is always 16MHz */
+#define HCLK_FRQ 16000000
+
static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
{
qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
@@ -65,6 +68,8 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
return;
}
+ system_clock_scale = NANOSECONDS_PER_SECOND / HCLK_FRQ;
+
object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
&error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) {