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| author | Hao Wu <wuhaotsh@google.com> | 2021-02-10 14:04:22 -0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-02-16 13:49:28 +0000 |
| commit | 94e778793954afc6ed47ef8e161044c79488e446 (patch) | |
| tree | b00da3b67b101fffd0a438a50d063f7c6a698a69 /hw/arm/npcm7xx_boards.c | |
| parent | 36cd5fbdbf4e1cb540d479e9b1708cdd81dac298 (diff) | |
| download | qemu-94e778793954afc6ed47ef8e161044c79488e446.zip qemu-94e778793954afc6ed47ef8e161044c79488e446.tar.gz qemu-94e778793954afc6ed47ef8e161044c79488e446.tar.bz2 | |
hw/i2c: Implement NPCM7XX SMBus Module Single Mode
This commit implements the single-byte mode of the SMBus.
Each Nuvoton SoC has 16 System Management Bus (SMBus). These buses
compliant with SMBus and I2C protocol.
This patch implements the single-byte mode of the SMBus. In this mode,
the user sends or receives a byte each time. The SMBus device transmits
it to the underlying i2c device and sends an interrupt back to the QEMU
guest.
Reviewed-by: Doug Evans<dje@google.com>
Reviewed-by: Tyrong Ting<kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Corey Minyard <cminyard@mvista.com>
Message-id: 20210210220426.3577804-2-wuhaotsh@google.com
Acked-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/npcm7xx_boards.c')
0 files changed, 0 insertions, 0 deletions