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author | Peter Maydell <peter.maydell@linaro.org> | 2021-08-12 10:33:50 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2021-09-01 11:08:20 +0100 |
commit | 9bfaf3754b71b72296f24f73876da67cf43c3e10 (patch) | |
tree | 8be02d071292144d436ed6fb22ea46ac7e070ae2 /hw/arm/msf2-som.c | |
parent | a4b1e9d3f863a8dfbf28f5469dcc95a07c9ac105 (diff) | |
download | qemu-9bfaf3754b71b72296f24f73876da67cf43c3e10.zip qemu-9bfaf3754b71b72296f24f73876da67cf43c3e10.tar.gz qemu-9bfaf3754b71b72296f24f73876da67cf43c3e10.tar.bz2 |
hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property
Instead of passing the MSF2 SoC an integer property specifying the
CPU clock rate, pass it a Clock instead. This lets us wire that
clock up to the armv7m object.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Message-id: 20210812093356.1946-20-peter.maydell@linaro.org
Diffstat (limited to 'hw/arm/msf2-som.c')
-rw-r--r-- | hw/arm/msf2-som.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index 343ec97..396e8b9 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -29,6 +29,7 @@ #include "hw/boards.h" #include "hw/qdev-properties.h" #include "hw/arm/boot.h" +#include "hw/qdev-clock.h" #include "exec/address-spaces.h" #include "hw/arm/msf2-soc.h" @@ -49,6 +50,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine) BusState *spi_bus; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ddr = g_new(MemoryRegion, 1); + Clock *m3clk; if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { error_report("This board can only be used with CPU %s", @@ -72,7 +74,10 @@ static void emcraft_sf2_s2s010_init(MachineState *machine) * in Libero. CPU clock is divided by APB0 and APB1 divisors for * peripherals. Emcraft's SoM kit comes with these settings by default. */ - qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000); + /* This clock doesn't need migration because it is fixed-frequency */ + m3clk = clock_new(OBJECT(machine), "m3clk"); + clock_set_hz(m3clk, 142 * 1000000); + qdev_connect_clock_in(dev, "m3clk", m3clk); qdev_prop_set_uint32(dev, "apb0div", 2); qdev_prop_set_uint32(dev, "apb1div", 2); |