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authorAnthony Liguori <aliguori@us.ibm.com>2013-07-10 10:54:16 -0500
committerAnthony Liguori <aliguori@us.ibm.com>2013-07-10 10:54:16 -0500
commit51455c59ddc370612f6e070d8eb0e594aaa7ef24 (patch)
treea3044bd466cb3a548e6abad273663469bf68647a /hw/arm/boot.c
parent9f9a03b9818194da39c6759d9b0cbee5d7ace4e1 (diff)
parent91b1df8cf9e1ecaa8679c9ea8713d1e25c28e6c4 (diff)
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Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into staging
QOM CPUState refactorings * Fix for OpenRISCCPU subclasses * Fix for gdbstub CPU selection * Move linux-user CPU functions into new header * CPUState part 10 refactoring: first_cpu, next_cpu, cpu_single_env et al. * Fix some targets to consistently inline TCG code generation * Centrally log CPU reset # gpg: Signature made Wed 10 Jul 2013 07:52:39 AM CDT using RSA key ID 3E7E013F # gpg: Can't check signature: public key not found # By Andreas Färber (41) and others # Via Andreas Färber * afaerber/tags/qom-cpu-for-anthony: (43 commits) cpu: Move reset logging to CPUState target-ppc: Change LOG_MMU_STATE() argument to CPUState target-i386: Change LOG_PCALL_STATE() argument to CPUState log: Change log_cpu_state[_mask]() argument to CPUState target-i386: Change do_smm_enter() argument to X86CPU target-i386: Change do_interrupt_all() argument to X86CPU target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPU target-unicore32: Change gen_intermediate_code_internal() signature target-sparc: Change gen_intermediate_code_internal() argument to SPARCCPU target-sh4: Change gen_intermediate_code_internal() argument to SuperHCPU target-s390x: Change gen_intermediate_code_internal() argument to S390CPU target-ppc: Change gen_intermediate_code_internal() argument to PowerPCCPU target-mips: Change gen_intermediate_code_internal() argument to MIPSCPU target-microblaze: Change gen_intermediate_code_internal() argument types target-m68k: Change gen_intermediate_code_internal() argument to M68kCPU target-lm32: Change gen_intermediate_code_internal() argument to LM32CPU target-i386: Change gen_intermediate_code_internal() argument to X86CPU target-cris: Change gen_intermediate_code_internal() argument to CRISCPU target-arm: Change gen_intermediate_code_internal() argument to ARMCPU target-alpha: Change gen_intermediate_code_internal() argument to AlphaCPU ...
Diffstat (limited to 'hw/arm/boot.c')
-rw-r--r--hw/arm/boot.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 3e8741e..a2e4032 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -333,7 +333,7 @@ static void do_cpu_reset(void *opaque)
env->regs[15] = info->entry & 0xfffffffe;
env->thumb = info->entry & 1;
} else {
- if (env == first_cpu) {
+ if (CPU(cpu) == first_cpu) {
env->regs[15] = info->loader_start;
if (!info->dtb_filename) {
if (old_param) {
@@ -351,7 +351,7 @@ static void do_cpu_reset(void *opaque)
void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
{
- CPUARMState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
int kernel_size;
int initrd_size;
int n;
@@ -470,9 +470,9 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
}
info->is_linux = is_linux;
- for (; env; env = env->next_cpu) {
- cpu = arm_env_get_cpu(env);
- env->boot_info = info;
+ for (; cs; cs = cs->next_cpu) {
+ cpu = ARM_CPU(cs);
+ cpu->env.boot_info = info;
qemu_register_reset(do_cpu_reset, cpu);
}
}