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| author | Peter Maydell <peter.maydell@linaro.org> | 2015-01-27 11:15:09 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-01-27 11:15:10 +0000 |
| commit | 7baef630732a50fcbb7ca5b1e9cc0ecf4f2998c9 (patch) | |
| tree | dc174613fe64f12f8c704c4c5de9f1e79f131957 /hw/acpi/ich9.c | |
| parent | 1ac0206b2ae1ffaeec564f110664a3a77bafafd2 (diff) | |
| parent | 0953225588ee30de2e92485331ad1bb3d7c7d089 (diff) | |
| download | qemu-7baef630732a50fcbb7ca5b1e9cc0ecf4f2998c9.zip qemu-7baef630732a50fcbb7ca5b1e9cc0ecf4f2998c9.tar.gz qemu-7baef630732a50fcbb7ca5b1e9cc0ecf4f2998c9.tar.bz2 | |
Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20150127' into staging
tricore bugfixes and RR1, RR2, RRPW and RRR insn
# gpg: Signature made Tue 27 Jan 2015 12:02:06 GMT using RSA key ID 6B69CA14
# gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>"
* remotes/bkoppelmann/tags/pull-tricore-20150127:
target-tricore: Add instructions of RRR opcode format
target-tricore: Add instructions of RRPW opcode format
target-tricore: Add instructions of RR2 opcode format
target-tricore: Add instructions of RR1 opcode format, that have 0x93 as first opcode
target-tricore: split up suov32 into suov32_pos and suov32_neg
target-tricore: Fix bugs found by coverity
target-tricore: calculate av bits before saturation
target-tricore: Several translator and cpu model fixes
target-tricore: Add missing ULL suffix on 64 bit constant
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/acpi/ich9.c')
0 files changed, 0 insertions, 0 deletions