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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-03-20 12:56:42 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-03-20 12:56:42 +0000 |
| commit | 32f70d7659986ab73665cfa67b7d3913901cdb3b (patch) | |
| tree | 5fa5e7f187a69de72eaea3ae70f209a18cf841d4 /fpu | |
| parent | 00e7c07b06d004cf54b19724f82afde8a7a37f37 (diff) | |
| parent | b28b3377d7e9ba35611d454d5a63ef50cab1f8c5 (diff) | |
| download | qemu-32f70d7659986ab73665cfa67b7d3913901cdb3b.zip qemu-32f70d7659986ab73665cfa67b7d3913901cdb3b.tar.gz qemu-32f70d7659986ab73665cfa67b7d3913901cdb3b.tar.bz2 | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170320' into staging
target-arm queue:
* fix MSR/MRS decoding for M profile CPUs
# gpg: Signature made Mon 20 Mar 2017 12:53:26 GMT
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20170320:
arm: Fix APSR writes via M profile MSR
arm: Enforce should-be-1 bits in MRS decoding
arm: Don't decode MRS(banked) or MSR(banked) for M profile
arm: HVC and SMC encodings don't exist for M profile
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'fpu')
0 files changed, 0 insertions, 0 deletions