ColdFire target.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2196 c046a42c-6fe2-441c-8c8c-71466251a162

4 files changed, 31 insertions, 0 deletions

diff --git a/fpu/softfloat-native.c b/fpu/softfloat-native.c
index bbdb3d6..1ef7cf2 100644
--- a/fpu/softfloat-native.c
+++ b/fpu/softfloat-native.c
@@ -221,6 +221,11 @@ float128 float64_to_float128( float64 a STATUS_PARAM)
 /*----------------------------------------------------------------------------
 | Software IEC/IEEE double-precision operations.
 *----------------------------------------------------------------------------*/
+float64 float64_trunc_to_int( float64 a STATUS_PARAM )
+{
+    return trunc(a);
+}
+
 float64 float64_round_to_int( float64 a STATUS_PARAM )
 {
 #if defined(__arm__)
@@ -289,6 +294,17 @@ char float64_is_signaling_nan( float64 a1)
 
 }
 
+char float64_is_nan( float64 a1 )
+{
+    float64u u;
+    uint64_t a;
+    u.f = a1;
+    a = u.i;
+
+    return ( LIT64( 0xFFE0000000000000 ) < (bits64) ( a<<1 ) );
+
+}
+
 #ifdef FLOATX80
 
 /*----------------------------------------------------------------------------
diff --git a/fpu/softfloat-native.h b/fpu/softfloat-native.h
index e7c08b8..05cf023 100644
--- a/fpu/softfloat-native.h
+++ b/fpu/softfloat-native.h
@@ -214,6 +214,7 @@ float128 float64_to_float128( float64 STATUS_PARAM );
 | Software IEC/IEEE double-precision operations.
 *----------------------------------------------------------------------------*/
 float64 float64_round_to_int( float64 STATUS_PARAM );
+float64 float64_trunc_to_int( float64 STATUS_PARAM );
 INLINE float64 float64_add( float64 a, float64 b STATUS_PARAM)
 {
     return a + b;
@@ -265,6 +266,7 @@ INLINE char float64_unordered( float64 a, float64 b STATUS_PARAM)
 char float64_compare( float64, float64 STATUS_PARAM );
 char float64_compare_quiet( float64, float64 STATUS_PARAM );
 char float64_is_signaling_nan( float64 );
+flag float64_is_nan( float64 );
 
 INLINE float64 float64_abs(float64 a)
 {
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 5e84620..f24913a 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -2483,6 +2483,17 @@ float64 float64_round_to_int( float64 a STATUS_PARAM )
 
 }
 
+float64 float64_trunc_to_int( float64 a STATUS_PARAM)
+{
+    int oldmode;
+    float64 res;
+    oldmode = STATUS(float_rounding_mode);
+    STATUS(float_rounding_mode) = float_round_to_zero;
+    res = float64_round_to_int(a STATUS_VAR);
+    STATUS(float_rounding_mode) = oldmode;
+    return res;
+}
+
 /*----------------------------------------------------------------------------
 | Returns the result of adding the absolute values of the double-precision
 | floating-point values `a' and `b'.  If `zSign' is 1, the sum is negated
diff --git a/fpu/softfloat.h b/fpu/softfloat.h
index fdc80f3..3dec119 100644
--- a/fpu/softfloat.h
+++ b/fpu/softfloat.h
@@ -237,6 +237,7 @@ char float32_lt_quiet( float32, float32 STATUS_PARAM );
 char float32_compare( float32, float32 STATUS_PARAM );
 char float32_compare_quiet( float32, float32 STATUS_PARAM );
 char float32_is_signaling_nan( float32 );
+flag float64_is_nan( float64 a );
 
 INLINE float32 float32_abs(float32 a)
 {
@@ -269,6 +270,7 @@ float128 float64_to_float128( float64 STATUS_PARAM );
 | Software IEC/IEEE double-precision operations.
 *----------------------------------------------------------------------------*/
 float64 float64_round_to_int( float64 STATUS_PARAM );
+float64 float64_trunc_to_int( float64 STATUS_PARAM );
 float64 float64_add( float64, float64 STATUS_PARAM );
 float64 float64_sub( float64, float64 STATUS_PARAM );
 float64 float64_mul( float64, float64 STATUS_PARAM );