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| author | Fernando Luis Vázquez Cao <fernando_b1@lab.ntt.co.jp> | 2013-12-06 17:33:01 +0900 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2013-12-12 13:13:11 +0100 |
| commit | 0522604b09b8cff54ba2450a7478da2a4d084817 (patch) | |
| tree | ef01436f7636715f9c4ad3c241b1cfe36e4c2e03 /exec.c | |
| parent | f86746c263753cf7a7e4bdb8829c70272dfcf36c (diff) | |
| download | qemu-0522604b09b8cff54ba2450a7478da2a4d084817.zip qemu-0522604b09b8cff54ba2450a7478da2a4d084817.tar.gz qemu-0522604b09b8cff54ba2450a7478da2a4d084817.tar.bz2 | |
target-i386: clear guest TSC on reset
VCPU TSC is not cleared by a warm reset (*), which leaves some types of Linux
guests (non-pvops guests and those with the kernel parameter no-kvmclock set)
vulnerable to the overflow in cyc2ns_offset fixed by upstream commit
9993bc635d01a6ee7f6b833b4ee65ce7c06350b1 ("sched/x86: Fix overflow in
cyc2ns_offset").
To put it in a nutshell, if such a Linux guest without the patch above applied
has been up more than 208 days and attempts a warm reset chances are that
the newly booted kernel will panic or hang.
(*) Intel Xeon E5 processors show the same broken behavior due to
the errata "TSC is Not Affected by Warm Reset" (Intel® Xeon®
Processor E5 Family Specification Update - August 2013): "The
TSC (Time Stamp Counter MSR 10H) should be cleared on
reset. Due to this erratum the TSC is not affected by warm
reset."
Cc: Will Auld <will.auld@intel.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Fernando Luis Vazquez Cao <fernando@oss.ntt.co.jp>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Fernando Luis Vázquez Cao <fernando_b1@lab.ntt.co.jp>
Diffstat (limited to 'exec.c')
0 files changed, 0 insertions, 0 deletions