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| author | Frederic Barrat <fbarrat@linux.ibm.com> | 2023-06-01 14:13:28 +0200 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2023-06-10 10:19:24 -0300 |
| commit | 32af01f83a763ccbba39c1cbc424e1b724d233df (patch) | |
| tree | 417c109b72f0b91495f4c8dfcec2b1935f02e542 /event-loop-base.c | |
| parent | cce84fc9193e2566b4f7f9de5a13e7ed360d44d9 (diff) | |
| download | qemu-32af01f83a763ccbba39c1cbc424e1b724d233df.zip qemu-32af01f83a763ccbba39c1cbc424e1b724d233df.tar.gz qemu-32af01f83a763ccbba39c1cbc424e1b724d233df.tar.bz2 | |
pnv/xive2: Add definition for the ESB cache configuration register
Add basic read/write support for the ESB cache configuration register
on P10. We don't model the ESB cache in qemu so reading/writing the
register won't do anything, but it avoids logging a guest error when
skiboot configures it:
qemu-system-ppc64 -machine powernv10 ... -d guest_errors
...
XIVE[0] - VC: invalid read @240
XIVE[0] - VC: invalid write @240
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230601121331.487207-3-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'event-loop-base.c')
0 files changed, 0 insertions, 0 deletions