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authorPeter Maydell <peter.maydell@linaro.org>2020-05-07 16:18:19 +0100
committerPeter Maydell <peter.maydell@linaro.org>2020-05-21 20:00:18 +0100
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docs/system: Document Musca boards
Provide a minimal documentation of the Musca boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200507151819.28444-6-peter.maydell@linaro.org
Diffstat (limited to 'docs')
-rw-r--r--docs/system/arm/musca.rst31
-rw-r--r--docs/system/target-arm.rst1
2 files changed, 32 insertions, 0 deletions
diff --git a/docs/system/arm/musca.rst b/docs/system/arm/musca.rst
new file mode 100644
index 0000000..81e3dc9
--- /dev/null
+++ b/docs/system/arm/musca.rst
@@ -0,0 +1,31 @@
+Arm Musca boards (``musca-a``, ``musca-b1``)
+============================================
+
+The Arm Musca development boards are a reference implementation
+of a system using the SSE-200 Subsystem for Embedded. They are
+dual Cortex-M33 systems.
+
+QEMU provides models of the A and B1 variants of this board.
+
+Unimplemented devices:
+
+- SPI
+- |I2C|
+- |I2S|
+- PWM
+- QSPI
+- Timer
+- SCC
+- GPIO
+- eFlash
+- MHU
+- PVT
+- SDIO
+- CryptoCell
+
+Note that (like the real hardware) the Musca-A machine is
+asymmetric: CPU 0 does not have the FPU or DSP extensions,
+but CPU 1 does. Also like the real hardware, the memory maps
+for the A and B1 variants differ significantly, so guest
+software must be built for the right variant.
+
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
index f2d9366..dce384c 100644
--- a/docs/system/target-arm.rst
+++ b/docs/system/target-arm.rst
@@ -77,6 +77,7 @@ undocumented; you can get a complete list by running
arm/integratorcp
arm/mps2
+ arm/musca
arm/realview
arm/versatile
arm/vexpress