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author | Peter Maydell <peter.maydell@linaro.org> | 2020-06-05 23:31:31 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2020-06-05 23:31:31 +0100 |
commit | 5a922419feb980592ef3dc16d74f0d9cf5ca4830 (patch) | |
tree | be787fd6c31f64df88940eff91672ddd62f0e3d8 /docs | |
parent | 175198ad91d8bac540159705873b4ffe4fb94eab (diff) | |
parent | 2c35a39eda0b16c2ed85c94cec204bf5efb97812 (diff) | |
download | qemu-5a922419feb980592ef3dc16d74f0d9cf5ca4830.zip qemu-5a922419feb980592ef3dc16d74f0d9cf5ca4830.tar.gz qemu-5a922419feb980592ef3dc16d74f0d9cf5ca4830.tar.bz2 |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200605' into staging
target-arm queue:
hw/ssi/imx_spi: Handle tx burst lengths other than 8 correctly
hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask()
hw/arm/pxa2xx: Replace printf() call by qemu_log_mask()
target/arm: Convert crypto insns to gvec
hw/adc/stm32f2xx_adc: Correct memory region size and access size
tests/acceptance: Add a boot test for the xlnx-versal-virt machine
docs/system: Document Aspeed boards
raspi: Add model of the USB controller
target/arm: Convert 2-reg-and-shift and 1-reg-imm Neon insns to decodetree
# gpg: Signature made Fri 05 Jun 2020 17:48:39 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20200605: (29 commits)
target/arm: Convert Neon one-register-and-immediate insns to decodetree
target/arm: Convert VCVT fixed-point ops to decodetree
target/arm: Convert Neon VSHLL, VMOVL to decodetree
target/arm: Convert Neon narrowing shifts with op==9 to decodetree
target/arm: Convert Neon narrowing shifts with op==8 to decodetree
target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree
target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree
target/arm: Convert Neon VSHR 2-reg-shift insns to decodetree
target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree
raspi2 acceptance test: add test for dwc-hsotg (dwc2) USB host
wire in the dwc-hsotg (dwc2) USB host controller emulation
usb: add short-packet handling to usb-storage driver
dwc-hsotg (dwc2) USB host controller emulation
dwc-hsotg (dwc2) USB host controller state definitions
dwc-hsotg (dwc2) USB host controller register definitions
raspi: add BCM2835 SOC MPHI emulation
docs/system: Document Aspeed boards
tests/acceptance: Add a boot test for the xlnx-versal-virt machine
hw/adc/stm32f2xx_adc: Correct memory region size and access size
target/arm: Split helper_crypto_sm3tt
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'docs')
-rw-r--r-- | docs/system/arm/aspeed.rst | 85 | ||||
-rw-r--r-- | docs/system/target-arm.rst | 1 |
2 files changed, 86 insertions, 0 deletions
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst new file mode 100644 index 0000000..45f891e --- /dev/null +++ b/docs/system/arm/aspeed.rst @@ -0,0 +1,85 @@ +Aspeed family boards (``*-bmc``, ``ast2500-evb``, ``ast2600-evb``) +================================================================== + +The QEMU Aspeed machines model BMCs of various OpenPOWER systems and +Aspeed evaluation boards. They are based on different releases of the +Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the +AST2500 with an ARM1176JZS CPU (800MHz) and more recently the AST2600 +with dual cores ARM Cortex A7 CPUs (1.2GHz). + +The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C, +etc. + +AST2400 SoC based machines : + +- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC + +AST2500 SoC based machines : + +- ``ast2500-evb`` Aspeed AST2500 Evaluation board +- ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC +- ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC +- ``sonorapass-bmc`` OCP SonoraPass BMC +- ``swift-bmc`` OpenPOWER Swift BMC POWER9 + +AST2600 SoC based machines : + +- ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex A7) +- ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC + +Supported devices +----------------- + + * SMP (for the AST2600 Cortex-A7) + * Interrupt Controller (VIC) + * Timer Controller + * RTC Controller + * I2C Controller + * System Control Unit (SCU) + * SRAM mapping + * X-DMA Controller (basic interface) + * Static Memory Controller (SMC or FMC) - Only SPI Flash support + * SPI Memory Controller + * USB 2.0 Controller + * SD/MMC storage controllers + * SDRAM controller (dummy interface for basic settings and training) + * Watchdog Controller + * GPIO Controller (Master only) + * UART + * Ethernet controllers + + +Missing devices +--------------- + + * Coprocessor support + * ADC (out of tree implementation) + * PWM and Fan Controller + * LPC Bus Controller + * Slave GPIO Controller + * Super I/O Controller + * Hash/Crypto Engine + * PCI-Express 1 Controller + * Graphic Display Controller + * PECI Controller + * MCTP Controller + * Mailbox Controller + * Virtual UART + * eSPI Controller + * I3C Controller + +Boot options +------------ + +The Aspeed machines can be started using the -kernel option to load a +Linux kernel or from a firmare image which can be downloaded from the +OpenPOWER jenkins : + + https://openpower.xyz/ + +The image should be attached as an MTD drive. Run : + +.. code-block:: bash + + $ qemu-system-arm -M romulus-bmc -nic user \ + -drive file=flash-romulus,format=raw,if=mtd -nographic diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index dce384c..1bd477a 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -81,6 +81,7 @@ undocumented; you can get a complete list by running arm/realview arm/versatile arm/vexpress + arm/aspeed arm/musicpal arm/nseries arm/orangepi |