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authorPeter Maydell <peter.maydell@linaro.org>2014-01-31 00:23:27 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-01-31 00:23:27 +0000
commit0159a64397fc8e6c85de73613d83a3612c840664 (patch)
tree8e321079516adf569b8bb59c0822a331d7e41e55 /docs
parent97374ce538883af677fd94803b71df2d55a9a4de (diff)
parenta75143eda2ddf581b51e96c000974bcdfe2cbd10 (diff)
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Merge remote-tracking branch 'mst/tags/for_anthony' into staging
acpi,pci,pc,virtio fixes and enhancements This includes new unit-tests for acpi by Marcel, hotplug for pci bridges by myself (piix only so far) and cpu hotplug for q35. And a bunch of fixes all over the place as usual. I included the patch to fix memory alignment for q35 as well - even though it limits 32 bit guests to 3G (they previously could address more memory with PAE). To remove the limit, this will have to be fixed in seabios. I also added self as virtio co-maintainer so I don't need to troll the list for patches to review. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Sun 26 Jan 2014 11:12:09 GMT using RSA key ID D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * mst/tags/for_anthony: (35 commits) MAINTAINERS: add self as virtio co-maintainer q35: document gigabyte_align q35: gigabyte alignment for ram acpi: Fix PCI hole handling on build_srat() pc: Save size of RAM below 4GB hw/pci: fix error flow in pci multifunction init acpi-test: update expected AML since recent changes pc: ACPI: update acpi-dsdt.hex.generated q35-acpi-dsdt.hex.generated pc: ACPI: unify source of CPU hotplug IO base/len pc: ACPI: expose PRST IO range via _CRS pc: Q35 DSDT: exclude CPU hotplug IO range from PCI bus resources pc: PIIX DSDT: exclude CPU/PCI hotplug & GPE0 IO range from PCI bus resources pc: set PRST base in DSDT depending on chipset acpi: ich9: add CPU hotplug handling to Q35 machine acpi: factor out common cpu hotplug code for PIIX4/Q35 acpi-build: enable hotplug for PCI bridges piix4: add acpi pci hotplug support pcihp: generalization of piix4 acpi pci: add pci_for_each_bus_depth_first pc: make: fix dependencies: rebuild when included file is changed ... Message-id: 1390735289-15563-1-git-send-email-mst@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'docs')
-rw-r--r--docs/specs/acpi_cpu_hotplug.txt4
1 files changed, 3 insertions, 1 deletions
diff --git a/docs/specs/acpi_cpu_hotplug.txt b/docs/specs/acpi_cpu_hotplug.txt
index f6f5774..340b751 100644
--- a/docs/specs/acpi_cpu_hotplug.txt
+++ b/docs/specs/acpi_cpu_hotplug.txt
@@ -10,7 +10,9 @@ ACPI GPE block (IO ports 0xafe0-0xafe3, byte access):
Generic ACPI GPE block. Bit 2 (GPE.2) used to notify CPU
hot-add/remove event to ACPI BIOS, via SCI interrupt.
-CPU present bitmap (IO port 0xaf00-0xaf1f, 1-byte access):
+CPU present bitmap for:
+ ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access)
+ PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access)
---------------------------------------------------------------
One bit per CPU. Bit position reflects corresponding CPU APIC ID.
Read-only.