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authorPeter Collingbourne <pcc@google.com>2021-06-16 12:56:14 -0700
committerPeter Maydell <peter.maydell@linaro.org>2021-06-24 14:58:48 +0100
commit86f0d4c7290eb2b21ec3eb44956ec245441275db (patch)
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parent4f57ef959cf83cc780658c7e97ba5f737aa666f2 (diff)
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target/arm: Implement MTE3
MTE3 introduces an asymmetric tag checking mode, in which loads are checked synchronously and stores are checked asynchronously. Add support for it. Signed-off-by: Peter Collingbourne <pcc@google.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210616195614.11785-1-pcc@google.com [PMM: Add line to emulation.rst] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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-rw-r--r--docs/system/arm/emulation.rst1
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diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 836c1ca..144dc49 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -29,6 +29,7 @@ the following architecture extensions:
- FEAT_LSE (Large System Extensions)
- FEAT_MTE (Memory Tagging Extension)
- FEAT_MTE2 (Memory Tagging Extension)
+- FEAT_MTE3 (MTE Asymmetric Fault Handling)
- FEAT_PAN (Privileged access never)
- FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN)
- FEAT_PAuth (Pointer authentication)