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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-03-01 11:59:50 -1000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-03-02 19:27:37 +0000 |
| commit | 7a928f43d8724bdf0777d7fc67a5ad973a0bf4bf (patch) | |
| tree | bda1102a1e105baa0947a7fb761fba733834e7af /docs/multi-thread-compression.txt | |
| parent | 0af312b6edd231e1c8d0dec12494a80bc39ac761 (diff) | |
| download | qemu-7a928f43d8724bdf0777d7fc67a5ad973a0bf4bf.zip qemu-7a928f43d8724bdf0777d7fc67a5ad973a0bf4bf.tar.gz qemu-7a928f43d8724bdf0777d7fc67a5ad973a0bf4bf.tar.bz2 | |
target/arm: Implement FEAT_LPA
This feature widens physical addresses (and intermediate physical
addresses for 2-stage translation) from 48 to 52 bits, when using
64k pages. The only thing left at this point is to handle the
extra bits in the TTBR and in the table descriptors.
Note that PAR_EL1 and HPFAR_EL2 are nominally extended, but we don't
mask out the high bits when writing to those registers, so no changes
are required there.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'docs/multi-thread-compression.txt')
0 files changed, 0 insertions, 0 deletions