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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-05-23 17:35:35 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-06-13 17:28:22 +1000 |
| commit | 2a2b221b65f5a4bcbbb9b508cdb76ff527e48aa6 (patch) | |
| tree | 944fed504408a69e7b5880696cd75b50bcb58673 /disas | |
| parent | 454c2201005b5f47a76116ab529c923e194ec615 (diff) | |
| download | qemu-2a2b221b65f5a4bcbbb9b508cdb76ff527e48aa6.zip qemu-2a2b221b65f5a4bcbbb9b508cdb76ff527e48aa6.tar.gz qemu-2a2b221b65f5a4bcbbb9b508cdb76ff527e48aa6.tar.bz2 | |
disas/riscv.c: Support disas for Zcm* extensions
Support disas for Zcmt* instructions only when related extensions
are supported.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'disas')
| -rw-r--r-- | disas/riscv.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/disas/riscv.c b/disas/riscv.c index f2dd5fd..6659f92 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -2505,7 +2505,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) op = rv_op_c_sqsp; } else { op = rv_op_c_fsdsp; - if (((inst >> 12) & 0b01)) { + if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) { switch ((inst >> 8) & 0b01111) { case 8: if (((inst >> 4) & 0b01111) >= 4) { @@ -2531,6 +2531,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) } else { switch ((inst >> 10) & 0b011) { case 0: + if (!dec->cfg->ext_zcmt) { + break; + } if (((inst >> 2) & 0xFF) >= 32) { op = rv_op_cm_jalt; } else { @@ -2538,6 +2541,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) } break; case 3: + if (!dec->cfg->ext_zcmp) { + break; + } switch ((inst >> 5) & 0b011) { case 1: op = rv_op_cm_mvsa01; break; case 3: op = rv_op_cm_mva01s; break; |