diff options
author | Michael Tokarev <mjt@tls.msk.ru> | 2014-02-15 20:26:25 +0000 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-15 20:26:30 +0000 |
commit | 0dbcf95a1ea5a5ca6222765ff8813c2cc17e8abd (patch) | |
tree | 449b5592ec9e5b02abef6e170f69e6c28ab7c643 /disas | |
parent | 078a1c37cad0d11d93ff8102f7653ce6109bb62d (diff) | |
download | qemu-0dbcf95a1ea5a5ca6222765ff8813c2cc17e8abd.zip qemu-0dbcf95a1ea5a5ca6222765ff8813c2cc17e8abd.tar.gz qemu-0dbcf95a1ea5a5ca6222765ff8813c2cc17e8abd.tar.bz2 |
libvixl: fix 64bit constants usage
Since commit 999b53ec8794f203964db3ecf939a3da5c4bc843:
Author: Claudio Fontana <claudio.fontana@linaro.org>
Date: Wed Feb 5 17:27:28 2014 +0000
disas: Implement disassembly output for A64
Use libvixl to implement disassembly output in debug
logs for A64, for use with both AArch64 hosts and targets.
disas/libvixl/ contains functions which uses 64bit constants
without using appropriate suffixes, which fails on 32bits.
Fix this by using ULL suffix.
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'disas')
-rw-r--r-- | disas/libvixl/a64/disasm-a64.cc | 16 | ||||
-rw-r--r-- | disas/libvixl/utils.cc | 20 |
2 files changed, 21 insertions, 15 deletions
diff --git a/disas/libvixl/a64/disasm-a64.cc b/disas/libvixl/a64/disasm-a64.cc index 4a49748..5c6b898 100644 --- a/disas/libvixl/a64/disasm-a64.cc +++ b/disas/libvixl/a64/disasm-a64.cc @@ -269,19 +269,19 @@ bool Disassembler::IsMovzMovnImm(unsigned reg_size, uint64_t value) { ((reg_size == kWRegSize) && (value <= 0xffffffff))); // Test for movz: 16 bits set at positions 0, 16, 32 or 48. - if (((value & 0xffffffffffff0000UL) == 0UL) || - ((value & 0xffffffff0000ffffUL) == 0UL) || - ((value & 0xffff0000ffffffffUL) == 0UL) || - ((value & 0x0000ffffffffffffUL) == 0UL)) { + if (((value & 0xffffffffffff0000ULL) == 0ULL) || + ((value & 0xffffffff0000ffffULL) == 0ULL) || + ((value & 0xffff0000ffffffffULL) == 0ULL) || + ((value & 0x0000ffffffffffffULL) == 0ULL)) { return true; } // Test for movn: NOT(16 bits set at positions 0, 16, 32 or 48). if ((reg_size == kXRegSize) && - (((value & 0xffffffffffff0000UL) == 0xffffffffffff0000UL) || - ((value & 0xffffffff0000ffffUL) == 0xffffffff0000ffffUL) || - ((value & 0xffff0000ffffffffUL) == 0xffff0000ffffffffUL) || - ((value & 0x0000ffffffffffffUL) == 0x0000ffffffffffffUL))) { + (((value & 0xffffffffffff0000ULL) == 0xffffffffffff0000ULL) || + ((value & 0xffffffff0000ffffULL) == 0xffffffff0000ffffULL) || + ((value & 0xffff0000ffffffffULL) == 0xffff0000ffffffffULL) || + ((value & 0x0000ffffffffffffULL) == 0x0000ffffffffffffULL))) { return true; } if ((reg_size == kWRegSize) && diff --git a/disas/libvixl/utils.cc b/disas/libvixl/utils.cc index 6f85e61..a45fb95 100644 --- a/disas/libvixl/utils.cc +++ b/disas/libvixl/utils.cc @@ -95,7 +95,7 @@ int CountSetBits(uint64_t value, int width) { ASSERT((width == 32) || (width == 64)); // Mask out unused bits to ensure that they are not counted. - value &= (0xffffffffffffffffUL >> (64-width)); + value &= (0xffffffffffffffffULL >> (64-width)); // Add up the set bits. // The algorithm works by adding pairs of bit fields together iteratively, @@ -108,12 +108,18 @@ int CountSetBits(uint64_t value, int width) { // value = h+g+f+e d+c+b+a // \ | // value = h+g+f+e+d+c+b+a - value = ((value >> 1) & 0x5555555555555555) + (value & 0x5555555555555555); - value = ((value >> 2) & 0x3333333333333333) + (value & 0x3333333333333333); - value = ((value >> 4) & 0x0f0f0f0f0f0f0f0f) + (value & 0x0f0f0f0f0f0f0f0f); - value = ((value >> 8) & 0x00ff00ff00ff00ff) + (value & 0x00ff00ff00ff00ff); - value = ((value >> 16) & 0x0000ffff0000ffff) + (value & 0x0000ffff0000ffff); - value = ((value >> 32) & 0x00000000ffffffff) + (value & 0x00000000ffffffff); + value = ((value >> 1) & 0x5555555555555555ULL) + + (value & 0x5555555555555555ULL); + value = ((value >> 2) & 0x3333333333333333ULL) + + (value & 0x3333333333333333ULL); + value = ((value >> 4) & 0x0f0f0f0f0f0f0f0fULL) + + (value & 0x0f0f0f0f0f0f0f0fULL); + value = ((value >> 8) & 0x00ff00ff00ff00ffULL) + + (value & 0x00ff00ff00ff00ffULL); + value = ((value >> 16) & 0x0000ffff0000ffffULL) + + (value & 0x0000ffff0000ffffULL); + value = ((value >> 32) & 0x00000000ffffffffULL) + + (value & 0x00000000ffffffffULL); return value; } |