diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2020-01-30 14:18:45 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-01-30 14:18:45 +0000 |
| commit | 204aa60b37c23a89e690d418f49787d274303ca7 (patch) | |
| tree | 902d059da93888c408d17ede0d92a1038cd4ff67 /disas/mips.c | |
| parent | a09a2b5a4d85d4bf2f04b0e503d7dd7905967148 (diff) | |
| parent | 99029be1c2875cd857614397674bbf563ddb6f91 (diff) | |
| download | qemu-204aa60b37c23a89e690d418f49787d274303ca7.zip qemu-204aa60b37c23a89e690d418f49787d274303ca7.tar.gz qemu-204aa60b37c23a89e690d418f49787d274303ca7.tar.bz2 | |
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jan-29-2020' into staging
MIPS queue for January 29th, 2020
# gpg: Signature made Wed 29 Jan 2020 18:29:43 GMT
# gpg: using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [full]
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65
* remotes/amarkovic/tags/mips-queue-jan-29-2020:
target/mips: Add implementation of GINVT instruction
target/mips: Amend CP0 WatchHi register implementation
hw/core/loader: Let load_elf() populate a field with CPU-specific flags
target/mips: semihosting: Remove 'uhi_done' label in helper_do_semihosting()
disas: Add a field for target-dependant data to disassemble_info
target/mips: Rectify documentation on deprecating MIPS r4k machine
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'disas/mips.c')
| -rw-r--r-- | disas/mips.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/disas/mips.c b/disas/mips.c index dfefe5e..b9a5204 100644 --- a/disas/mips.c +++ b/disas/mips.c @@ -1409,6 +1409,16 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dvp", "t", 0x41600024, 0xffe0ffff, TRAP|WR_t, 0, I32R6}, {"evp", "", 0x41600004, 0xffffffff, TRAP, 0, I32R6}, {"evp", "t", 0x41600004, 0xffe0ffff, TRAP|WR_t, 0, I32R6}, +{"ginvi", "v", 0x7c00003d, 0xfc1ffcff, TRAP | INSN_TLB, 0, I32R6}, +{"ginvt", "v", 0x7c0000bd, 0xfc1ffcff, TRAP | INSN_TLB, 0, I32R6}, +{"crc32b", "t,v,t", 0x7c00000f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6}, +{"crc32h", "t,v,t", 0x7c00004f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6}, +{"crc32w", "t,v,t", 0x7c00008f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6}, +{"crc32d", "t,v,t", 0x7c0000cf, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I64R6}, +{"crc32cb", "t,v,t", 0x7c00010f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6}, +{"crc32ch", "t,v,t", 0x7c00014f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6}, +{"crc32cw", "t,v,t", 0x7c00018f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6}, +{"crc32cd", "t,v,t", 0x7c0001cf, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I64R6}, /* MSA */ {"sll.b", "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, |