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author | Peter Crosthwaite <crosthwaitepeter@gmail.com> | 2015-09-10 22:39:41 -0700 |
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committer | Paolo Bonzini <pbonzini@redhat.com> | 2015-09-16 17:33:33 +0200 |
commit | 9a13565d52bfd321934fb44ee004bbaf5f5913a8 (patch) | |
tree | 8255a8d1fead4dfa15e021ef2343ad312d65ba70 /cputlb.c | |
parent | 5f12a788c04cf36442f3be00ebf6fdc3b8c8c4ba (diff) | |
download | qemu-9a13565d52bfd321934fb44ee004bbaf5f5913a8.zip qemu-9a13565d52bfd321934fb44ee004bbaf5f5913a8.tar.gz qemu-9a13565d52bfd321934fb44ee004bbaf5f5913a8.tar.bz2 |
cputlb: move CPU_LOOP() for tlb_reset() to exec.c
To prepare for multi-arch, cputlb.c should only have awareness of one
single architecture. This means it should not have access to the full
CPU lists which may be heterogeneous. Instead, push the CPU_LOOP() up
to the one and only caller in exec.c.
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-Id: <db06dc6c49f8970caaf116d0385f00ee10a56f2f.1441614289.git.crosthwaite.peter@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'cputlb.c')
-rw-r--r-- | cputlb.c | 27 |
1 files changed, 12 insertions, 15 deletions
@@ -262,27 +262,24 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) return ram_addr; } -void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length) +void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) { - CPUState *cpu; CPUArchState *env; - CPU_FOREACH(cpu) { - int mmu_idx; + int mmu_idx; - env = cpu->env_ptr; - for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - unsigned int i; + env = cpu->env_ptr; + for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { + unsigned int i; - for (i = 0; i < CPU_TLB_SIZE; i++) { - tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], - start1, length); - } + for (i = 0; i < CPU_TLB_SIZE; i++) { + tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], + start1, length); + } - for (i = 0; i < CPU_VTLB_SIZE; i++) { - tlb_reset_dirty_range(&env->tlb_v_table[mmu_idx][i], - start1, length); - } + for (i = 0; i < CPU_VTLB_SIZE; i++) { + tlb_reset_dirty_range(&env->tlb_v_table[mmu_idx][i], + start1, length); } } } |