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authorbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2003-07-29 20:53:01 +0000
committerbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2003-07-29 20:53:01 +0000
commitb6d78bfa0dc11a7a23cb7ccc9b00b217e6fb68fe (patch)
tree1277b63f1b009b779040781fff8cc554448ea9f4 /cpu-i386.h
parentc33a346edff5910dddeea84792b73cb117518911 (diff)
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correct CPL support (should fix flat real mode support)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@343 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'cpu-i386.h')
-rw-r--r--cpu-i386.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/cpu-i386.h b/cpu-i386.h
index 82cdffc..879ab1e 100644
--- a/cpu-i386.h
+++ b/cpu-i386.h
@@ -256,6 +256,7 @@ typedef struct CPUX86State {
SegmentCache tr;
SegmentCache gdt; /* only base and limit are used */
SegmentCache idt; /* only base and limit are used */
+ int cpl; /* current cpl */
/* sysenter registers */
uint32_t sysenter_cs;
@@ -276,6 +277,7 @@ typedef struct CPUX86State {
uint32_t breakpoints[MAX_BREAKPOINTS];
int nb_breakpoints;
+ int singlestep_enabled;
/* user data */
void *opaque;
@@ -298,6 +300,12 @@ int cpu_x86_get_pic_interrupt(CPUX86State *s);
/* needed to load some predefinied segment registers */
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
+/* wrapper, just in case memory mappings must be changed */
+static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
+{
+ s->cpl = cpl;
+}
+
/* simulate fsave/frstor */
void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);