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| author | Richard Henderson <rth@twiddle.net> | 2011-04-18 15:09:09 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@anchor.twiddle.net> | 2011-05-31 10:18:05 -0700 |
| commit | 6a80e088c70b88f844ed90b78f4ce987c43ec522 (patch) | |
| tree | 71da5cd011715a126943b47903a684ef553e2c4e /cpu-exec.c | |
| parent | a18ad89351dd6c828b7fe33fafd1764cef61a40d (diff) | |
| download | qemu-6a80e088c70b88f844ed90b78f4ce987c43ec522.zip qemu-6a80e088c70b88f844ed90b78f4ce987c43ec522.tar.gz qemu-6a80e088c70b88f844ed90b78f4ce987c43ec522.tar.bz2 | |
target-alpha: Disable interrupts properly.
Interrupts are disabled in PALmode, and when the PS IL is high enough.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'cpu-exec.c')
| -rw-r--r-- | cpu-exec.c | 33 |
1 files changed, 30 insertions, 3 deletions
@@ -488,9 +488,36 @@ int cpu_exec(CPUState *env1) next_tb = 0; } #elif defined(TARGET_ALPHA) - if (interrupt_request & CPU_INTERRUPT_HARD) { - do_interrupt(env); - next_tb = 0; + { + int idx = -1; + /* ??? This hard-codes the OSF/1 interrupt levels. */ + switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) { + case 0 ... 3: + if (interrupt_request & CPU_INTERRUPT_HARD) { + idx = EXCP_DEV_INTERRUPT; + } + /* FALLTHRU */ + case 4: + if (interrupt_request & CPU_INTERRUPT_TIMER) { + idx = EXCP_CLK_INTERRUPT; + } + /* FALLTHRU */ + case 5: + if (interrupt_request & CPU_INTERRUPT_SMP) { + idx = EXCP_SMP_INTERRUPT; + } + /* FALLTHRU */ + case 6: + if (interrupt_request & CPU_INTERRUPT_MCHK) { + idx = EXCP_MCHK; + } + } + if (idx >= 0) { + env->exception_index = idx; + env->error_code = 0; + do_interrupt(env); + next_tb = 0; + } } #elif defined(TARGET_CRIS) if (interrupt_request & CPU_INTERRUPT_HARD |