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| author | Michael Walle <michael@walle.cc> | 2011-02-17 23:45:02 +0100 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2011-03-07 13:42:36 +0100 |
| commit | 81ea0e130470bb307e5ab7e2d71e7b80b46ef1bf (patch) | |
| tree | 12fa76fd965b4a318cbef7c5b5eac76ff0b2d652 /cpu-exec.c | |
| parent | ca27c052d992da83ce0786d81f85b87cd1f5d301 (diff) | |
| download | qemu-81ea0e130470bb307e5ab7e2d71e7b80b46ef1bf.zip qemu-81ea0e130470bb307e5ab7e2d71e7b80b46ef1bf.tar.gz qemu-81ea0e130470bb307e5ab7e2d71e7b80b46ef1bf.tar.bz2 | |
LatticeMico32 target support
This patch adds support for the LatticeMico32 softcore processor by Lattice
Semiconductor.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Diffstat (limited to 'cpu-exec.c')
| -rw-r--r-- | cpu-exec.c | 13 |
1 files changed, 12 insertions, 1 deletions
@@ -239,6 +239,7 @@ int cpu_exec(CPUState *env1) #elif defined(TARGET_ALPHA) #elif defined(TARGET_ARM) #elif defined(TARGET_PPC) +#elif defined(TARGET_LM32) #elif defined(TARGET_MICROBLAZE) #elif defined(TARGET_MIPS) #elif defined(TARGET_SH4) @@ -292,6 +293,8 @@ int cpu_exec(CPUState *env1) env->old_exception = -1; #elif defined(TARGET_PPC) do_interrupt(env); +#elif defined(TARGET_LM32) + do_interrupt(env); #elif defined(TARGET_MICROBLAZE) do_interrupt(env); #elif defined(TARGET_MIPS) @@ -332,7 +335,7 @@ int cpu_exec(CPUState *env1) } #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \ - defined(TARGET_MICROBLAZE) + defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) if (interrupt_request & CPU_INTERRUPT_HALT) { env->interrupt_request &= ~CPU_INTERRUPT_HALT; env->halted = 1; @@ -412,6 +415,13 @@ int cpu_exec(CPUState *env1) env->interrupt_request &= ~CPU_INTERRUPT_HARD; next_tb = 0; } +#elif defined(TARGET_LM32) + if ((interrupt_request & CPU_INTERRUPT_HARD) + && (env->ie & IE_IE)) { + env->exception_index = EXCP_IRQ; + do_interrupt(env); + next_tb = 0; + } #elif defined(TARGET_MICROBLAZE) if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sregs[SR_MSR] & MSR_IE) @@ -624,6 +634,7 @@ int cpu_exec(CPUState *env1) /* XXX: Save/restore host fpu exception state?. */ #elif defined(TARGET_SPARC) #elif defined(TARGET_PPC) +#elif defined(TARGET_LM32) #elif defined(TARGET_M68K) cpu_m68k_flush_flags(env, env->cc_op); env->cc_op = CC_OP_FLAGS; |