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authorDavid Hoover <spm@boiteauxlettres.sent.at>2014-09-12 14:06:47 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-09-12 14:06:47 +0100
commitc3c8d6b3ddc881fb2ebd651e320cda36b2ec079b (patch)
treec05da2ccb0ac4652634c3bfa54f917763900c99c /cpu-exec.c
parentf022b8e95379b0433d13509706b66f38fc15dde8 (diff)
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cpu-exec.c: Allow disabling of IRQs on ARM Cortex-M CPUs
Correct an error in the logic for deciding whether we can take an IRQ interrupt which meant that on M profile cores it was never possible to disable them. The design here is still bogus in that M profile doesn't have separate "IRQ" and "FIQ", which are an A/R profile concept; we should ideally implement the proper priority based scheme. Signed-off-by: David Hoover <spm@boiteauxlettres.sent.at> [PMM: Wrote a proper commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'cpu-exec.c')
-rw-r--r--cpu-exec.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu-exec.c b/cpu-exec.c
index 7b5d2e2..e9adf56 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -618,8 +618,8 @@ int cpu_exec(CPUArchState *env)
We avoid this by disabling interrupts when
pc contains a magic address. */
if (interrupt_request & CPU_INTERRUPT_HARD
- && ((IS_M(env) && env->regs[15] < 0xfffffff0)
- || !(env->daif & PSTATE_I))) {
+ && !(env->daif & PSTATE_I)
+ && (!IS_M(env) || env->regs[15] < 0xfffffff0)) {
cpu->exception_index = EXCP_IRQ;
cc->do_interrupt(cpu);
next_tb = 0;