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author | Jia Liu <proljc@gmail.com> | 2012-07-20 15:50:41 +0800 |
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committer | Blue Swirl <blauwirbel@gmail.com> | 2012-07-27 21:12:57 +0000 |
commit | b6a71ef7e01bcac7aeb47d8de4082704fbc6479c (patch) | |
tree | 3ae466a65ec1083a2575b5d3cbb92139e9b98742 /cpu-exec.c | |
parent | 726fe04572093504e7bf4ea56e0b2de559063787 (diff) | |
download | qemu-b6a71ef7e01bcac7aeb47d8de4082704fbc6479c.zip qemu-b6a71ef7e01bcac7aeb47d8de4082704fbc6479c.tar.gz qemu-b6a71ef7e01bcac7aeb47d8de4082704fbc6479c.tar.bz2 |
target-or32: Add interrupt support
Add OpenRISC interrupt support.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'cpu-exec.c')
-rw-r--r-- | cpu-exec.c | 17 |
1 files changed, 17 insertions, 0 deletions
@@ -388,6 +388,23 @@ int cpu_exec(CPUArchState *env) do_interrupt(env); next_tb = 0; } +#elif defined(TARGET_OPENRISC) + { + int idx = -1; + if ((interrupt_request & CPU_INTERRUPT_HARD) + && (env->sr & SR_IEE)) { + idx = EXCP_INT; + } + if ((interrupt_request & CPU_INTERRUPT_TIMER) + && (env->sr & SR_TEE)) { + idx = EXCP_TICK; + } + if (idx >= 0) { + env->exception_index = idx; + do_interrupt(env); + next_tb = 0; + } + } #elif defined(TARGET_SPARC) if (interrupt_request & CPU_INTERRUPT_HARD) { if (cpu_interrupts_enabled(env) && |