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author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-04-27 21:07:38 +0000 |
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committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-04-27 21:07:38 +0000 |
commit | fdf9b3e831e8e6b5ceb2a44c742da7d1ab558242 (patch) | |
tree | ba55ae7076148e88f174b9ce8928f12551583941 /cpu-exec.c | |
parent | 66a93e0f47fa9869178008c7bc38d66a7c5e45f4 (diff) | |
download | qemu-fdf9b3e831e8e6b5ceb2a44c742da7d1ab558242.zip qemu-fdf9b3e831e8e6b5ceb2a44c742da7d1ab558242.tar.gz qemu-fdf9b3e831e8e6b5ceb2a44c742da7d1ab558242.tar.bz2 |
sh4 target (Samuel Tardieu)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1861 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'cpu-exec.c')
-rw-r--r-- | cpu-exec.c | 63 |
1 files changed, 63 insertions, 0 deletions
@@ -190,6 +190,10 @@ static inline TranslationBlock *tb_find_fast(void) flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); cs_base = 0; pc = env->PC; +#elif defined(TARGET_SH4) + flags = env->sr & (SR_MD | SR_RB); + cs_base = 0; /* XXXXX */ + pc = env->pc; #else #error unsupported CPU #endif @@ -363,6 +367,8 @@ int cpu_exec(CPUState *env1) #endif #elif defined(TARGET_PPC) #elif defined(TARGET_MIPS) +#elif defined(TARGET_SH4) + /* XXXXX */ #else #error unsupported target CPU #endif @@ -407,6 +413,8 @@ int cpu_exec(CPUState *env1) do_interrupt(env->exception_index); #elif defined(TARGET_ARM) do_interrupt(env); +#elif defined(TARGET_SH4) + do_interrupt(env); #endif } env->exception_index = -1; @@ -550,6 +558,8 @@ int cpu_exec(CPUState *env1) env->exception_index = EXCP_IRQ; do_interrupt(env); } +#elif defined(TARGET_SH4) + /* XXXXX */ #endif if (env->interrupt_request & CPU_INTERRUPT_EXITTB) { env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; @@ -608,6 +618,8 @@ int cpu_exec(CPUState *env1) cpu_dump_state(env, logfile, fprintf, 0); #elif defined(TARGET_MIPS) cpu_dump_state(env, logfile, fprintf, 0); +#elif defined(TARGET_SH4) + cpu_dump_state(env, logfile, fprintf, 0); #else #error unsupported target CPU #endif @@ -817,6 +829,8 @@ int cpu_exec(CPUState *env1) #endif #elif defined(TARGET_PPC) #elif defined(TARGET_MIPS) +#elif defined(TARGET_SH4) + /* XXXXX */ #else #error unsupported target CPU #endif @@ -1121,6 +1135,55 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address, return 1; } +#elif defined (TARGET_SH4) +static inline int handle_cpu_signal(unsigned long pc, unsigned long address, + int is_write, sigset_t *old_set, + void *puc) +{ + TranslationBlock *tb; + int ret; + + if (cpu_single_env) + env = cpu_single_env; /* XXX: find a correct solution for multithread */ +#if defined(DEBUG_SIGNAL) + printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", + pc, address, is_write, *(unsigned long *)old_set); +#endif + /* XXX: locking issue */ + if (is_write && page_unprotect(h2g(address), pc, puc)) { + return 1; + } + + /* see if it is an MMU fault */ + ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0); + if (ret < 0) + return 0; /* not an MMU fault */ + if (ret == 0) + return 1; /* the MMU fault was handled without causing real CPU fault */ + + /* now we have a real cpu fault */ + tb = tb_find_pc(pc); + if (tb) { + /* the PC is inside the translated code. It means that we have + a virtual CPU fault */ + cpu_restore_state(tb, env, pc, puc); + } + if (ret == 1) { +#if 0 + printf("PF exception: NIP=0x%08x error=0x%x %p\n", + env->nip, env->error_code, tb); +#endif + /* we restore the process signal mask as the sigreturn should + do it (XXX: use sigsetjmp) */ + sigprocmask(SIG_SETMASK, old_set, NULL); + // do_raise_exception_err(env->exception_index, env->error_code); + } else { + /* activate soft MMU for this block */ + cpu_resume_from_signal(env, puc); + } + /* never comes here */ + return 1; +} #else #error unsupported target CPU #endif |