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| author | Aurelien Jarno <aurelien@aurel32.net> | 2010-03-29 02:12:51 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-04-01 21:51:59 +0200 |
| commit | 477ba620018d51da23c60556b500118cb8d1d373 (patch) | |
| tree | 576ec2a29439ac69b71709437de5a23e3d5f57c0 /cpu-common.h | |
| parent | ebf50fb3b948ed2ef0c5802f8721044b78896427 (diff) | |
| download | qemu-477ba620018d51da23c60556b500118cb8d1d373.zip qemu-477ba620018d51da23c60556b500118cb8d1d373.tar.gz qemu-477ba620018d51da23c60556b500118cb8d1d373.tar.bz2 | |
tcg: initial ia64 support
A few words about design choices:
* On IA64, instructions should be grouped by bundle, and dependencies
between instructions declared. A first version of this code tried to
schedule instructions automatically, but was very complex and too
invasive for the current common TCG code (ops not ending at
instruction boundaries, code retranslation breaking already generated
code, etc.) It was also not very efficient, as dependencies between
TCG ops is not available.
Instead the option taken by the current implementation does not try
to fill the bundle by scheduling instructions, but by providing ops
not available as an ia64 instruction, and by offering 22-bit constant
loading for most of the instructions. With both options the bundle are
filled at approximately the same level.
* Up to 128 registers can be affected to a function on IA64, but TCG
limits this number to 64, which is actually more than enough. The
register affectation is the following:
- r0: used to map a constant argument with value 0
- r1: global pointer
- r2, r3: internal use
- r4 to r6: not used to avoid saving them
- r7: env structure
- r8 to r11: free for TCG (call clobbered)
- r12: stack pointer
- r13: thread pointer
- r14 to r31: free for TCG (call clobbered)
- r32: reserved (return address)
- r33: reserved (PFS)
- r33 to r63: free for TCG
* The IA64 architecture has only 64-bit registers and no 32-bit
instructions (the only exception being cmp4). Therefore 64-bit
registers and instructions are used for 32-bit ops. The adopted
strategy is the same as the ABI, that is the higher 32 bits are
undefined. Most ops (and, or, add, shl, etc.) can directly use
the 64-bit registers, while some others have to sign-extend (sar,
div, etc.) or zero-extend (shr, divu, etc.) the register first.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'cpu-common.h')
| -rw-r--r-- | cpu-common.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu-common.h b/cpu-common.h index bb05300..ce0221b 100644 --- a/cpu-common.h +++ b/cpu-common.h @@ -3,7 +3,7 @@ /* CPU interfaces that are target indpendent. */ -#if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) +#if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) || defined(__ia64__) #define WORDS_ALIGNED #endif |