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author | David Hildenbrand <david@redhat.com> | 2019-02-22 11:19:48 +0100 |
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committer | David Hildenbrand <david@redhat.com> | 2019-06-07 14:53:25 +0200 |
commit | 9be6fa99d6b1371ced6a9b57c32daec86733cd0a (patch) | |
tree | d1922ea6cd6eadd8593e093d51daacbc50fc960e /contrib/ivshmem-client | |
parent | e19a61eb514dbf7c9a725c7539ce3b6166cd6ac4 (diff) | |
download | qemu-9be6fa99d6b1371ced6a9b57c32daec86733cd0a.zip qemu-9be6fa99d6b1371ced6a9b57c32daec86733cd0a.tar.gz qemu-9be6fa99d6b1371ced6a9b57c32daec86733cd0a.tar.bz2 |
s390x/tcg: Introduce tcg_s390_vector_exception()
Handling is similar to data exceptions, however we can always store the
VXC into the lowore and the FPC:
z14 PoP, 6-20, "Vector-Exception Code"
When a vector-processing exception causes a pro-
gram interruption, a vector-exception code (VXC) is
stored at location 147, and zeros are stored at loca-
tions 144-146. The VXC is also placed in the DXC
field of the floating-point-control (FPC) register if bit
45 of control register 0 is one. When bit 45 of control
register 0 is zero and bit 46 of control register 0 is
one, the DXC field of the FPC register and the con-
tents of storage at location 147 are unpredictable.
Signed-off-by: David Hildenbrand <david@redhat.com>
Diffstat (limited to 'contrib/ivshmem-client')
0 files changed, 0 insertions, 0 deletions