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author | Michael Clark <mjc@sifive.com> | 2018-03-03 01:32:59 +1300 |
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committer | Michael Clark <mjc@sifive.com> | 2018-03-07 08:30:28 +1300 |
commit | 25fa194b7b11901561532e435beb83d046899f7a (patch) | |
tree | 361c143f38183b884bcac16e30d69791c3c40492 /configure | |
parent | a7240d1e4aac4cd4542d68f3cc722939550da6af (diff) | |
download | qemu-25fa194b7b11901561532e435beb83d046899f7a.zip qemu-25fa194b7b11901561532e435beb83d046899f7a.tar.gz qemu-25fa194b7b11901561532e435beb83d046899f7a.tar.bz2 |
RISC-V Build Infrastructure
This adds RISC-V into the build system enabling the following targets:
- riscv32-softmmu
- riscv64-softmmu
- riscv32-linux-user
- riscv64-linux-user
This adds defaults configs for RISC-V, enables the build for the RISC-V
CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'
script is updated to add the RISC-V ELF magic.
Expected checkpatch errors for consistency reasons:
ERROR: line over 90 characters
FILE: scripts/qemu-binfmt-conf.sh
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: Michael Clark <mjc@sifive.com>
Diffstat (limited to 'configure')
-rwxr-xr-x | configure | 13 |
1 files changed, 13 insertions, 0 deletions
@@ -6797,6 +6797,16 @@ case "$target_name" in echo "TARGET_ABI32=y" >> $config_target_mak gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml" ;; + riscv32) + TARGET_BASE_ARCH=riscv + TARGET_ABI_DIR=riscv + mttcg=yes + ;; + riscv64) + TARGET_BASE_ARCH=riscv + TARGET_ABI_DIR=riscv + mttcg=yes + ;; sh4|sh4eb) TARGET_ARCH=sh4 bflt="yes" @@ -6966,6 +6976,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do ppc*) disas_config "PPC" ;; + riscv) + disas_config "RISCV" + ;; s390*) disas_config "S390" ;; |