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| author | Joel Stanley <joel@jms.id.au> | 2019-11-19 15:12:03 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-12-16 10:46:34 +0000 |
| commit | 28c80f15fc9c4c1ee980e87e693374f196aa20fe (patch) | |
| tree | 803e45958f1b9fbee16adc86a0a3ea366da492e1 /bt-vhci.c | |
| parent | aabf1de4b7a2fb14797946f8eb970d391cecf0d8 (diff) | |
| download | qemu-28c80f15fc9c4c1ee980e87e693374f196aa20fe.zip qemu-28c80f15fc9c4c1ee980e87e693374f196aa20fe.tar.gz qemu-28c80f15fc9c4c1ee980e87e693374f196aa20fe.tar.bz2 | |
watchdog/aspeed: Fix AST2600 frequency behaviour
The AST2600 control register sneakily changed the meaning of bit 4
without anyone noticing. It no longer controls the 1MHz vs APB clock
select, and instead always runs at 1MHz.
The AST2500 was always 1MHz too, but it retained bit 4, making it read
only. We can model both using the same fixed 1MHz calculation.
Fixes: 6b2b2a703cad ("hw: wdt_aspeed: Add AST2600 support")
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-10-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'bt-vhci.c')
0 files changed, 0 insertions, 0 deletions