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| author | Artyom Tarasenko <atar4qemu@googlemail.com> | 2010-06-21 20:23:21 +0200 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2010-06-27 19:06:44 +0300 |
| commit | 94c5f455d3dc2222e0f793928eccf45ab968460e (patch) | |
| tree | ab20707707d56a5c3cf19324a09863a77eb3ae35 /balloon.c | |
| parent | 3a5c16fcb821beab17d9e0d334bda4927000180c (diff) | |
| download | qemu-94c5f455d3dc2222e0f793928eccf45ab968460e.zip qemu-94c5f455d3dc2222e0f793928eccf45ab968460e.tar.gz qemu-94c5f455d3dc2222e0f793928eccf45ab968460e.tar.bz2 | |
mask all interrupts when MASTER_DISABLE is set
The MASTER_DISABLE bit (aka mask-all) masks all the interrupts.
According to Sun-4M System Architecture
"The level–15 interrupt sources [...] are maskable with the Interrupt Target
Mask Register. While these interrupts are considered ’non–maskable’ within
the SPARC IU, a mask capability is provided to allow the boot firmware
to establish a basic environment before receiving any level–15 interrupts,
which are non–maskable within SPARC. A mask–all bit is provided to allow
disabling of all external interrupts during change of the CIT."
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'balloon.c')
0 files changed, 0 insertions, 0 deletions