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| author | Greg Kurz <groug@kaod.org> | 2019-12-04 20:43:48 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-12-17 10:39:48 +1100 |
| commit | c1ad0b892ce20cf2b5e619c79e8a0c4c66b235dc (patch) | |
| tree | b9f1a7ce3e3aeb3efb304d70e061645fcb8944d2 /authz | |
| parent | 4febcdd88f08422a66a1aa0dc55e1472abed3c4b (diff) | |
| download | qemu-c1ad0b892ce20cf2b5e619c79e8a0c4c66b235dc.zip qemu-c1ad0b892ce20cf2b5e619c79e8a0c4c66b235dc.tar.gz qemu-c1ad0b892ce20cf2b5e619c79e8a0c4c66b235dc.tar.bz2 | |
ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU models
The power7_set_irq() and power9_set_irq() functions set this but it is
never used actually. Modern Book3s compatible CPUs are only supported
by the pnv and spapr machines. They have an interrupt controller, XICS
for POWER7/8 and XIVE for POWER9, whose models don't require to track
IRQ input states at the CPU level.
Drop these lines to avoid confusion.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157548862861.3650476.16622818876928044450.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'authz')
0 files changed, 0 insertions, 0 deletions