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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-04-25 21:12:59 -0700 |
|---|---|---|
| committer | Alex Bennée <alex.bennee@linaro.org> | 2019-05-10 20:23:21 +0100 |
| commit | 4601f8d10d7628bcaf2a8179af36e04b42879e91 (patch) | |
| tree | 6d14d49a786fd41174ffd89de6b51f616fecee37 /accel | |
| parent | 2dd926067867c2dd19e66d31a7990e8eea7258f6 (diff) | |
| download | qemu-4601f8d10d7628bcaf2a8179af36e04b42879e91.zip qemu-4601f8d10d7628bcaf2a8179af36e04b42879e91.tar.gz qemu-4601f8d10d7628bcaf2a8179af36e04b42879e91.tar.bz2 | |
cputlb: Do unaligned store recursion to outermost function
This is less tricky than for loads, because we always fall
back to single byte stores to implement unaligned stores.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Diffstat (limited to 'accel')
| -rw-r--r-- | accel/tcg/cputlb.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e4d0c94..a083324 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1413,9 +1413,9 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, * Store Helpers */ -static void store_helper(CPUArchState *env, target_ulong addr, uint64_t val, - TCGMemOpIdx oi, uintptr_t retaddr, size_t size, - bool big_endian) +static inline void __attribute__((always_inline)) +store_helper(CPUArchState *env, target_ulong addr, uint64_t val, + TCGMemOpIdx oi, uintptr_t retaddr, size_t size, bool big_endian) { uintptr_t mmu_idx = get_mmuidx(oi); uintptr_t index = tlb_index(env, mmu_idx, addr); @@ -1514,7 +1514,7 @@ static void store_helper(CPUArchState *env, target_ulong addr, uint64_t val, /* Little-endian extract. */ val8 = val >> (i * 8); } - store_helper(env, addr + i, val8, oi, retaddr, 1, big_endian); + helper_ret_stb_mmu(env, addr + i, val8, oi, retaddr); } return; } |