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author | Richard Henderson <richard.henderson@linaro.org> | 2020-02-16 17:43:11 -0800 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2020-03-17 08:41:07 -0700 |
commit | 43d1ccd2a02fadf3c36b46a8c31125a28864d141 (patch) | |
tree | 2e7ce58febacb88c6cf0bdcbdff65a327d59e3a6 /accel | |
parent | 312b426fea4d6dd322d7472c80010a8ba7a166d2 (diff) | |
download | qemu-43d1ccd2a02fadf3c36b46a8c31125a28864d141.zip qemu-43d1ccd2a02fadf3c36b46a8c31125a28864d141.tar.gz qemu-43d1ccd2a02fadf3c36b46a8c31125a28864d141.tar.bz2 |
tcg: Remove CONFIG_VECTOR16
The comment in tcg-runtime-gvec.c about CONFIG_VECTOR16 says that
tcg-op-gvec.c has eliminated size 8 vectors, and only passes on
multiples of 16. This may have been true of the first few operations,
but is not true of all operations.
In particular, multiply, shift by scalar, and compare of 8- and 16-bit
elements are not expanded inline if host vector operations are not
supported.
For an x86_64 host that does not support AVX, this means that we will
fall back to the helper, which will attempt to use SSE instructions,
which will SEGV on an invalid 8-byte aligned memory operation.
This patch simply removes the CONFIG_VECTOR16 code and configuration
without further simplification.
Buglink: https://bugs.launchpad.net/bugs/1863508
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'accel')
-rw-r--r-- | accel/tcg/tcg-runtime-gvec.c | 35 |
1 files changed, 1 insertions, 34 deletions
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index 5b1902d..00da093 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -24,32 +24,6 @@ #include "tcg/tcg-gvec-desc.h" -/* Virtually all hosts support 16-byte vectors. Those that don't can emulate - * them via GCC's generic vector extension. This turns out to be simpler and - * more reliable than getting the compiler to autovectorize. - * - * In tcg-op-gvec.c, we asserted that both the size and alignment of the data - * are multiples of 16. - * - * When the compiler does not support all of the operations we require, the - * loops are written so that we can always fall back on the base types. - */ -#ifdef CONFIG_VECTOR16 -typedef uint8_t vec8 __attribute__((vector_size(16))); -typedef uint16_t vec16 __attribute__((vector_size(16))); -typedef uint32_t vec32 __attribute__((vector_size(16))); -typedef uint64_t vec64 __attribute__((vector_size(16))); - -typedef int8_t svec8 __attribute__((vector_size(16))); -typedef int16_t svec16 __attribute__((vector_size(16))); -typedef int32_t svec32 __attribute__((vector_size(16))); -typedef int64_t svec64 __attribute__((vector_size(16))); - -#define DUP16(X) { X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X } -#define DUP8(X) { X, X, X, X, X, X, X, X } -#define DUP4(X) { X, X, X, X } -#define DUP2(X) { X, X } -#else typedef uint8_t vec8; typedef uint16_t vec16; typedef uint32_t vec32; @@ -64,7 +38,6 @@ typedef int64_t svec64; #define DUP8(X) X #define DUP4(X) X #define DUP2(X) X -#endif /* CONFIG_VECTOR16 */ static inline void clear_high(void *d, intptr_t oprsz, uint32_t desc) { @@ -917,13 +890,7 @@ void HELPER(gvec_sar64v)(void *d, void *a, void *b, uint32_t desc) clear_high(d, oprsz, desc); } -/* If vectors are enabled, the compiler fills in -1 for true. - Otherwise, we must take care of this by hand. */ -#ifdef CONFIG_VECTOR16 -# define DO_CMP0(X) X -#else -# define DO_CMP0(X) -(X) -#endif +#define DO_CMP0(X) -(X) #define DO_CMP1(NAME, TYPE, OP) \ void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) \ |