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| author | Nick Hudson <skrll@netbsd.org> | 2020-05-16 16:41:47 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2020-06-02 08:42:37 -0700 |
| commit | 853d9a4be8c281547797249dd0d329d807fc7fd7 (patch) | |
| tree | a9a15162bed05a77397b12dc65c04bfb7dbb41d1 /accel/tcg | |
| parent | 61f15c487fc2aea14f6b0e52c459ae8b7d252a65 (diff) | |
| download | qemu-853d9a4be8c281547797249dd0d329d807fc7fd7.zip qemu-853d9a4be8c281547797249dd0d329d807fc7fd7.tar.gz qemu-853d9a4be8c281547797249dd0d329d807fc7fd7.tar.bz2 | |
accel/tcg: Adjust cpu_signal_handler for NetBSD/arm
Fix building on NetBSD/arm by extracting the FSR value from the
correct siginfo_t field.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nick Hudson <skrll@netbsd.org>
Message-Id: <20200516154147.24842-1-skrll@netbsd.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'accel/tcg')
| -rw-r--r-- | accel/tcg/user-exec.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 5235994..bc391eb 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -517,6 +517,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, #if defined(__NetBSD__) #include <ucontext.h> +#include <sys/siginfo.h> #endif int cpu_signal_handler(int host_signum, void *pinfo, @@ -525,10 +526,12 @@ int cpu_signal_handler(int host_signum, void *pinfo, siginfo_t *info = pinfo; #if defined(__NetBSD__) ucontext_t *uc = puc; + siginfo_t *si = pinfo; #else ucontext_t *uc = puc; #endif unsigned long pc; + uint32_t fsr; int is_write; #if defined(__NetBSD__) @@ -539,10 +542,17 @@ int cpu_signal_handler(int host_signum, void *pinfo, pc = uc->uc_mcontext.arm_pc; #endif - /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or - * later processor; on v5 we will always report this as a read). +#ifdef __NetBSD__ + fsr = si->si_trap; +#else + fsr = uc->uc_mcontext.error_code; +#endif + /* + * In the FSR, bit 11 is WnR, assuming a v6 or + * later processor. On v5 we will always report + * this as a read, which will fail later. */ - is_write = extract32(uc->uc_mcontext.error_code, 11, 1); + is_write = extract32(fsr, 11, 1); return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } |