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authorKONRAD Frederic <fred.konrad@greensocs.com>2017-02-03 16:32:12 +0100
committerEdgar E. Iglesias <edgar.iglesias@xilinx.com>2017-06-27 15:09:15 +0200
commit71b9a45330fe220d11a7a187efc477745dffbd26 (patch)
treef63add29216d923b1b0d59648e886bf3fb44e345 /accel/tcg
parentf2553f04890cfaef2fb045e7d19b9c4ecd414da2 (diff)
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cputlb: fix the way get_page_addr_code fills the tlb
get_page_addr_code(..) does a cpu_ldub_code to fill the tlb: This can lead to some side effects if a device is mapped at this address. So this patch replaces the cpu_memory_ld by a tlb_fill. Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'accel/tcg')
-rw-r--r--accel/tcg/cputlb.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 5d6c755..95265a0 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -849,8 +849,10 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr)
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
mmu_idx = cpu_mmu_index(env, true);
if (unlikely(env->tlb_table[mmu_idx][index].addr_code !=
- (addr & TARGET_PAGE_MASK))) {
- cpu_ldub_code(env, addr);
+ (addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)))) {
+ if (!VICTIM_TLB_HIT(addr_read, addr)) {
+ tlb_fill(ENV_GET_CPU(env), addr, MMU_INST_FETCH, mmu_idx, 0);
+ }
}
iotlbentry = &env->iotlb[mmu_idx][index];
pd = iotlbentry->addr & ~TARGET_PAGE_MASK;