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| author | Damien Hedde <damien.hedde@greensocs.com> | 2021-12-07 10:44:27 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-12-07 15:30:08 +0000 |
| commit | 2958e5150dfa297dd5a51fe57a29156b8744f07f (patch) | |
| tree | 44b2e93480aeea34b7e69ab0d6aaec6e8c111641 /accel/tcg/trace.h | |
| parent | 7635eff97104242d618400e4b6746d0a5c97af82 (diff) | |
| download | qemu-2958e5150dfa297dd5a51fe57a29156b8744f07f.zip qemu-2958e5150dfa297dd5a51fe57a29156b8744f07f.tar.gz qemu-2958e5150dfa297dd5a51fe57a29156b8744f07f.tar.bz2 | |
gicv3: fix ICH_MISR's LRENP computation
According to the "Arm Generic Interrupt Controller Architecture
Specification GIC architecture version 3 and 4" (version G: page 345
for aarch64 or 509 for aarch32):
LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and
ICH_HCR.EOIcount is non-zero.
When only LRENPIE was set (and EOI count was zero), the LRENP bit was
wrongly set and MISR value was wrong.
As an additional consequence, if an hypervisor set ICH_HCR.LRENPIE,
the maintenance interrupt was constantly fired. It happens since patch
9cee1efe92 ("hw/intc: Set GIC maintenance interrupt level to only 0 or 1")
which fixed another bug about maintenance interrupt (most significant
bits of misr, including this one, were ignored in the interrupt trigger).
Fixes: 83f036fe3d ("hw/intc/arm_gicv3: Add accessors for ICH_ system registers")
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20211207094427.3473-1-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'accel/tcg/trace.h')
0 files changed, 0 insertions, 0 deletions