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| author | Akihiko Odaki <akihiko.odaki@daynix.com> | 2023-05-23 11:43:36 +0900 |
|---|---|---|
| committer | Jason Wang <jasowang@redhat.com> | 2023-05-23 15:20:15 +0800 |
| commit | efb1fd7a73aac29b02514c8aa46b752a7c7caa73 (patch) | |
| tree | 0f9af6b8bfe29891a3d84bee44d2e11b7554adc8 /MAINTAINERS | |
| parent | 5844562b177e2067b8ebf78d1845334e0c759896 (diff) | |
| download | qemu-efb1fd7a73aac29b02514c8aa46b752a7c7caa73.zip qemu-efb1fd7a73aac29b02514c8aa46b752a7c7caa73.tar.gz qemu-efb1fd7a73aac29b02514c8aa46b752a7c7caa73.tar.bz2 | |
igb: Clear-on-read ICR when ICR.INTA is set
For GPIE.NSICR, Section 7.3.2.1.2 says:
> ICR bits are cleared on register read. If GPIE.NSICR = 0b, then the
> clear on read occurs only if no bit is set in the IMS or at least one
> bit is set in the IMS and there is a true interrupt as reflected in
> ICR.INTA.
e1000e does similar though it checks for CTRL_EXT.IAME, which does not
exist on igb.
Suggested-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Diffstat (limited to 'MAINTAINERS')
0 files changed, 0 insertions, 0 deletions