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author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-04-28 19:26:34 +0200 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2020-05-04 10:32:46 +0100 |
commit | e544f80030121040c8932ff1bd4006f390266c0f (patch) | |
tree | fc49c1dbf17f6b1937c3828f0f73bdb0690fb723 /LICENSE | |
parent | 5a89dd2385a193aa954a7c9bf4e381f2ba6ae359 (diff) | |
download | qemu-e544f80030121040c8932ff1bd4006f390266c0f.zip qemu-e544f80030121040c8932ff1bd4006f390266c0f.tar.gz qemu-e544f80030121040c8932ff1bd4006f390266c0f.tar.bz2 |
target/arm: Use uint64_t for midr field in CPU state struct
MIDR_EL1 is a 64-bit system register with the top 32-bit being RES0.
Represent it in QEMU's ARMCPU struct with a uint64_t, not a
uint32_t.
This fixes an error when compiling with -Werror=conversion
because we were manipulating the register value using a
local uint64_t variable:
target/arm/cpu64.c: In function ‘aarch64_max_initfn’:
target/arm/cpu64.c:628:21: error: conversion from ‘uint64_t’ {aka ‘long unsigned int’} to ‘uint32_t’ {aka ‘unsigned int’} may change value [-Werror=conversion]
628 | cpu->midr = t;
| ^
and future-proofs us against a possible future architecture
change using some of the top 32 bits.
Suggested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20200428172634.29707-1-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'LICENSE')
0 files changed, 0 insertions, 0 deletions