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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-08-22 14:23:56 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-09-14 11:19:40 +0100 |
| commit | 0b42f4fab9d3e994efa44e17cb76c15b269bcbda (patch) | |
| tree | ca700a981fda9bba6f7e671f2f71890e9f63eb53 /LICENSE | |
| parent | a793bcd0272d9d25c942184ee18c7ed4dc75dc0d (diff) | |
| download | qemu-0b42f4fab9d3e994efa44e17cb76c15b269bcbda.zip qemu-0b42f4fab9d3e994efa44e17cb76c15b269bcbda.tar.gz qemu-0b42f4fab9d3e994efa44e17cb76c15b269bcbda.tar.bz2 | |
target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits
FEAT_PMUv3p5 introduces new bits which disable the cycle
counter from counting:
* MDCR_EL2.HCCD disables the counter when in EL2
* MDCR_EL3.SCCD disables the counter when Secure
Add the code to support these bits.
(Note that there is a third documented counter-disable
bit, MDCR_EL3.MCCD, which disables the counter when in
EL3. This is not present until FEAT_PMUv3p7, so is
out of scope for now.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822132358.3524971-9-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'LICENSE')
0 files changed, 0 insertions, 0 deletions