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author | Peter Maydell <peter.maydell@linaro.org> | 2022-04-08 15:15:32 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2022-04-22 14:44:52 +0100 |
commit | 641be69745c49d3c35efb62ee41d21d701b210ba (patch) | |
tree | 3ab42b0ff9e8bfe524b4ba1d00c1149231fc3127 /COPYING | |
parent | ae3b3ba15c73320f75c121b08266a25a9e5d4edb (diff) | |
download | qemu-641be69745c49d3c35efb62ee41d21d701b210ba.zip qemu-641be69745c49d3c35efb62ee41d21d701b210ba.tar.gz qemu-641be69745c49d3c35efb62ee41d21d701b210ba.tar.bz2 |
hw/intc/arm_gicv3: Implement new GICv4 redistributor registers
Implement the new GICv4 redistributor registers: GICR_VPROPBASER
and GICR_VPENDBASER; for the moment we implement these as simple
reads-as-written stubs, together with the necessary migration
and reset handling.
We don't put ID-register checks on the handling of these registers,
because they are all in the only-in-v4 extra register frames, so
they're not accessible in a GICv3.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-24-peter.maydell@linaro.org
Diffstat (limited to 'COPYING')
0 files changed, 0 insertions, 0 deletions