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| author | Rajnesh Kanwal <rkanwal@rivosinc.com> | 2023-10-16 12:17:32 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-11-07 11:02:17 +1000 |
| commit | d17bcae5f7e9f949052a1f126a7f23e7279b6d96 (patch) | |
| tree | 4f7a0b3296e3b4a29055a16d9563ba243349383f | |
| parent | a7b69170254b15b5a40b318ed5559084ccfc466b (diff) | |
| download | qemu-d17bcae5f7e9f949052a1f126a7f23e7279b6d96.zip qemu-d17bcae5f7e9f949052a1f126a7f23e7279b6d96.tar.gz qemu-d17bcae5f7e9f949052a1f126a7f23e7279b6d96.tar.bz2 | |
target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.
RISCV_EXCP_SEMIHOST is set to 0x10, which can be a local interrupt id
as well. This change moves RISCV_EXCP_SEMIHOST to switch case so that
async flag check is performed before invoking semihosting logic.
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231016111736.28721-3-rkanwal@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu_helper.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8c28241..aaeb1d0 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1605,15 +1605,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong htval = 0; target_ulong mtval2 = 0; - if (cause == RISCV_EXCP_SEMIHOST) { - do_common_semihosting(cs); - env->pc += 4; - return; - } - if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { + case RISCV_EXCP_SEMIHOST: + do_common_semihosting(cs); + env->pc += 4; + return; case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: case RISCV_EXCP_LOAD_ADDR_MIS: |