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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-04-12 13:43:23 +0200 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | 9de7b7b5c7ca8e81c6d62b7c5c5a4753fa597bcb (patch) | |
| tree | c2cd7fe7381801f10b37caf8702b9a953a756aad | |
| parent | 02369f790676f8118b8f0769f58d5890e15fcd25 (diff) | |
| download | qemu-9de7b7b5c7ca8e81c6d62b7c5c5a4753fa597bcb.zip qemu-9de7b7b5c7ca8e81c6d62b7c5c5a4753fa597bcb.tar.gz qemu-9de7b7b5c7ca8e81c6d62b7c5c5a4753fa597bcb.tar.bz2 | |
target/riscv: Move hstatus.spvp check to check_access_hlsv
The current cpu_mmu_index value is really irrelevant to
the HLV/HSV lookup. Provide the correct priv level directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-16-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-16-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu_helper.c | 10 | ||||
| -rw-r--r-- | target/riscv/op_helper.c | 2 |
2 files changed, 2 insertions, 10 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9dfd1d7..ccba3c4 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -770,14 +770,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, use_background = true; } - /* - * MPRV does not affect the virtual-machine load/store - * instructions, HLV, HLVX, and HSV. - */ - if (mmuidx_2stage(mmu_idx)) { - mode = get_field(env->hstatus, HSTATUS_SPVP); - } - if (first_stage == false) { /* * We are in stage 2 translation, this is similar to stage 1. @@ -1250,7 +1242,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, * instructions, HLV, HLVX, and HSV. */ if (mmuidx_2stage(mmu_idx)) { - mode = get_field(env->hstatus, HSTATUS_SPVP); + ; } else if (mode == PRV_M && access_type != MMU_INST_FETCH && get_field(env->mstatus, MSTATUS_MPRV)) { mode = get_field(env->mstatus, MSTATUS_MPP); diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 6122f5f..f83f7b5 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } - return cpu_mmu_index(env, x) | MMU_2STAGE_BIT; + return get_field(env->hstatus, HSTATUS_SPVP) | MMU_2STAGE_BIT; } target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr) |