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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-02-27 11:33:22 -1000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-03-06 14:08:11 +0000 |
| commit | fdfb214cf05a186e573fc337972d5b169edc942a (patch) | |
| tree | f47a57f4ec6f09948bbbb4a18e14defc5f6cca84 | |
| parent | 5cd5fa756e177cb293d44e02b5f6194f83c528bb (diff) | |
| download | qemu-fdfb214cf05a186e573fc337972d5b169edc942a.zip qemu-fdfb214cf05a186e573fc337972d5b169edc942a.tar.gz qemu-fdfb214cf05a186e573fc337972d5b169edc942a.tar.bz2 | |
target/arm: Fix svep width in arm_gen_dynamic_svereg_xml
Define svep based on the size of the predicates,
not the primary vector registers.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/gdbstub64.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 895e19f..d0e1305 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -297,7 +297,7 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) /* Create the predicate vector type. */ g_string_append_printf(s, "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>", - reg_width / 8); + pred_width / 8); /* Define the vector registers. */ for (i = 0; i < 32; i++) { |