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authorPranith Kumar <bobby.prani@gmail.com>2016-07-14 16:20:21 -0400
committerRichard Henderson <rth@twiddle.net>2016-09-16 08:12:11 -0700
commitf8f03b3707b49898052fb8cd75ee31d19c8161fc (patch)
tree5a00614f5b93e95c1608c03e5da71f2280c04b1f
parentc9314d610e0e5da4d2cd5a36f3563d102b3294e0 (diff)
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tcg/sparc: Add support for fence
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> Message-Id: <20160714202026.9727-10-bobby.prani@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
-rw-r--r--tcg/sparc/tcg-target.inc.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
index 92f8818..700c434 100644
--- a/tcg/sparc/tcg-target.inc.c
+++ b/tcg/sparc/tcg-target.inc.c
@@ -249,6 +249,8 @@ static const int tcg_target_call_oarg_regs[] = {
#define STWA (INSN_OP(3) | INSN_OP3(0x14))
#define STXA (INSN_OP(3) | INSN_OP3(0x1e))
+#define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13))
+
#ifndef ASI_PRIMARY_LITTLE
#define ASI_PRIMARY_LITTLE 0x88
#endif
@@ -835,6 +837,12 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)
tcg_out_nop(s);
}
+static void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ /* Note that the TCG memory order constants mirror the Sparc MEMBAR. */
+ tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL));
+}
+
#ifdef CONFIG_SOFTMMU
static tcg_insn_unit *qemu_ld_trampoline[16];
static tcg_insn_unit *qemu_st_trampoline[16];
@@ -1466,6 +1474,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c);
break;
+ case INDEX_op_mb:
+ tcg_out_mb(s, a0);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
@@ -1567,6 +1579,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_qemu_st_i32, { "sZ", "A" } },
{ INDEX_op_qemu_st_i64, { "SZ", "A" } },
+ { INDEX_op_mb, { } },
{ -1 },
};