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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-10-01 21:29:10 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-10-25 01:01:13 -0700 |
| commit | e8325dc02d059685331d8607d5e620328bac594e (patch) | |
| tree | 245905e9d7752250ccb022b8281f5624db69391b | |
| parent | 5d617bfba070b6c771ed7a0cdfb238bfe7bd1a33 (diff) | |
| download | qemu-e8325dc02d059685331d8607d5e620328bac594e.zip qemu-e8325dc02d059685331d8607d5e620328bac594e.tar.gz qemu-e8325dc02d059685331d8607d5e620328bac594e.tar.bz2 | |
target/sparc: Move RDTBR, FLUSHW to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | target/sparc/insns.decode | 5 | ||||
| -rw-r--r-- | target/sparc/translate.c | 23 |
2 files changed, 16 insertions, 12 deletions
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 7d91a7b..0b6f4c9 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -76,6 +76,11 @@ RDPR_gl 10 rd:5 101010 10000 0 0000000000000 RDPR_strand_status 10 rd:5 101010 11010 0 0000000000000 RDPR_ver 10 rd:5 101010 11111 0 0000000000000 +{ + FLUSHW 10 00000 101011 00000 0 0000000000000 + RDTBR 10 rd:5 101011 00000 0 0000000000000 +} + Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 { # For v7, the entire simm13 field is present, but masked to 7 bits. diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 6e415d7..67d3292 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -39,6 +39,7 @@ #ifdef TARGET_SPARC64 # define gen_helper_rdpsr(D, E) qemu_build_not_reached() #else +# define gen_helper_flushw(E) qemu_build_not_reached() # define gen_helper_rdccr(D, E) qemu_build_not_reached() # define gen_helper_rdcwp(D, E) qemu_build_not_reached() # define gen_helper_tick_get_count(D, E, T, C) qemu_build_not_reached() @@ -3464,6 +3465,7 @@ static TCGv do_rdtba(DisasContext *dc, TCGv dst) return cpu_tbr; } +TRANS(RDTBR, 32, do_rd_special, supervisor(dc), a->rd, do_rdtba) TRANS(RDPR_tba, 64, do_rd_special, supervisor(dc), a->rd, do_rdtba) static TCGv do_rdpstate(DisasContext *dc, TCGv dst) @@ -3562,6 +3564,15 @@ static TCGv do_rdver(DisasContext *dc, TCGv dst) TRANS(RDPR_ver, 64, do_rd_special, supervisor(dc), a->rd, do_rdver) +static bool trans_FLUSHW(DisasContext *dc, arg_FLUSHW *a) +{ + if (avail_64(dc)) { + gen_helper_flushw(tcg_env); + return advance_pc(dc); + } + return false; +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -3592,18 +3603,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) TCGv cpu_dst __attribute__((unused)) = tcg_temp_new(); TCGv cpu_tmp0 __attribute__((unused)); -#if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY) - if (xop == 0x2b) { /* rdtbr / V9 flushw */ -#ifdef TARGET_SPARC64 - gen_helper_flushw(tcg_env); -#else - if (!supervisor(dc)) - goto priv_insn; - gen_store_gpr(dc, rd, cpu_tbr); -#endif - break; - } -#endif if (xop == 0x34) { /* FPU Operations */ if (gen_trap_ifnofpu(dc)) { goto jmp_insn; |