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| author | Alex Bennée <alex.bennee@linaro.org> | 2018-07-19 16:42:48 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2018-07-19 09:07:31 -0700 |
| commit | e65a5f227d77a5dbae7a7123c3ee915ee4bd80cf (patch) | |
| tree | fb7d6cd6c6e919299e7c3ab0521cc13fa64530bf | |
| parent | e1ea55668ffe6ce558a063f3a9621b761738e1f2 (diff) | |
| download | qemu-e65a5f227d77a5dbae7a7123c3ee915ee4bd80cf.zip qemu-e65a5f227d77a5dbae7a7123c3ee915ee4bd80cf.tar.gz qemu-e65a5f227d77a5dbae7a7123c3ee915ee4bd80cf.tar.bz2 | |
tcg/aarch64: limit mul_vec size
In AdvSIMD we can only do 32x32 integer multiples although SVE is
capable of larger 64 bit multiples. As a result we can end up
generating invalid opcodes. Fix this by only reprting we can emit
mul vector ops if the size is small enough.
Fixes a crash on:
sve-all-short-v8.3+sve@vq3/insn_mul_z_zi___INC.risu.bin
When running on AArch64 hardware.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20180719154248.29669-1-alex.bennee@linaro.org>
[rth: Removed the tcg_debug_assert -- there are plenty of other
cases that we do not diagnose within the insn encoding helpers.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | tcg/aarch64/tcg-target.inc.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 4562d36..083592a 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -2219,7 +2219,6 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) switch (opc) { case INDEX_op_add_vec: case INDEX_op_sub_vec: - case INDEX_op_mul_vec: case INDEX_op_and_vec: case INDEX_op_or_vec: case INDEX_op_xor_vec: @@ -2232,6 +2231,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_shri_vec: case INDEX_op_sari_vec: return 1; + case INDEX_op_mul_vec: + return vece < MO_64; default: return 0; |