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| author | Peter Maydell <peter.maydell@linaro.org> | 2018-06-29 17:21:22 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2018-07-02 08:02:20 -0700 |
| commit | e4c967a7201400d7f76e5847d5b4c4ac9e2566e0 (patch) | |
| tree | 2fa74c6eba35a6a4daf82757764794d2a3414466 | |
| parent | 334692bce7f0653a93b8d84ecde8c847b08dec38 (diff) | |
| download | qemu-e4c967a7201400d7f76e5847d5b4c4ac9e2566e0.zip qemu-e4c967a7201400d7f76e5847d5b4c4ac9e2566e0.tar.gz qemu-e4c967a7201400d7f76e5847d5b4c4ac9e2566e0.tar.bz2 | |
accel/tcg: Correct "is this a TLB miss" check in get_page_addr_code()
In commit 71b9a45330fe220d1 we changed the condition we use
to determine whether we need to refill the TLB in
get_page_addr_code() to
if (unlikely(env->tlb_table[mmu_idx][index].addr_code !=
(addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)))) {
This isn't the right check (it will falsely fail if the
input addr happens to have the low bit corresponding to
TLB_INVALID_MASK set, for instance). Replace it with a
use of the new tlb_hit() function, which is the correct test.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20180629162122.19376-3-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | accel/tcg/cputlb.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index adb7119..3ae1198 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -957,8 +957,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx = cpu_mmu_index(env, true); - if (unlikely(env->tlb_table[mmu_idx][index].addr_code != - (addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)))) { + if (unlikely(!tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr))) { if (!VICTIM_TLB_HIT(addr_read, addr)) { tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0); } |