diff options
| author | Lara Lazier <laramglazier@gmail.com> | 2021-06-16 14:39:07 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2021-06-16 15:02:41 +0200 |
| commit | e0375ec760d3c49163eb16f272349dc16f13e59c (patch) | |
| tree | 30d94fedcaa725c1db41b687f41228181287c895 | |
| parent | 498df2a7470e09d6cb0204f45eeb30d7ae796465 (diff) | |
| download | qemu-e0375ec760d3c49163eb16f272349dc16f13e59c.zip qemu-e0375ec760d3c49163eb16f272349dc16f13e59c.tar.gz qemu-e0375ec760d3c49163eb16f272349dc16f13e59c.tar.bz2 | |
target/i386: Added Intercept CR0 writes check
When the selective CR0 write intercept is set, all writes to bits in
CR0 other than CR0.TS or CR0.MP cause a VMEXIT.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Message-Id: <20210616123907.17765-5-laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | target/i386/tcg/sysemu/misc_helper.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c index 0cef2f1..db0d8a9 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -84,6 +84,15 @@ void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) { switch (reg) { case 0: + /* + * If we reach this point, the CR0 write intercept is disabled. + * But we could still exit if the hypervisor has requested the selective + * intercept for bits other than TS and MP + */ + if (cpu_svm_has_intercept(env, SVM_EXIT_CR0_SEL_WRITE) && + ((env->cr[0] ^ t0) & ~(CR0_TS_MASK | CR0_MP_MASK))) { + cpu_vmexit(env, SVM_EXIT_CR0_SEL_WRITE, 0, GETPC()); + } cpu_x86_update_cr0(env, t0); break; case 3: |